LGMT with one murmur:
> +;; Floating-point version with length and mask
> +(define_expand "<cbranch_optab><mode>"
> + [(set (pc)
> + (unspec:V_VLSF
> + [(if_then_else
> + (match_operator 0 "riscv_cbranch_comparison_operator"
> + [(match_operand:<VM> 1 "register_operand")
> + (match_operand:V_VLSF 2 "register_operand")
> + (match_operand:V_VLSF 3 "register_operand")
> + (match_operand 4 "autovec_length_operand")
> + (match_operand 5 "const_0_operand")])
> + (label_ref (match_operand 6 ""))
> + (pc))]
> + COND_LEN_CBRANCH_CMP))]
> + "TARGET_VECTOR"
> +{
> + rtx_code code = GET_CODE (operands[0]);
> + rtx mask = gen_reg_rtx (<VM>mode);
> +
> + rtx tmp = gen_reg_rtx (<VM>mode);
> + riscv_vector::expand_vec_cmp_float (tmp, code, operands[2], operands[3],
> + false);
I just found the latest argument is always false in the RISC-V
backend...we may consider simplifying that later, but it's definitely
not a blocker for this patch.
