On Fri, Nov 28, 2025 at 07:23:13PM +0100, Andreas Schwab wrote: > This breaks bootstrap for riscv: > > In file included from ../../gcc/rtl.h:4039, > from ../../gcc/config/riscv/riscv.cc:33: > ../../gcc/config/riscv/riscv.cc: In function 'rtx_def* > riscv_unspec_address_offset(rtx, rtx, riscv_symbol_type)': > ../../gcc/config/riscv/riscv.cc:2817:47: error: arithmetic between different > enumeration types 'unspec' and 'riscv_symbol_type' is deprecated > [-Werror=deprecated-enum-enum-conversion] > 2817 | UNSPEC_ADDRESS_FIRST + symbol_type); > | ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~ > ./genrtl.h:502:43: note: in definition of macro 'gen_rtx_fmt_Ei' > 502 | gen_rtx_fmt_Ei_stat ((c), (m), (arg0), (arg1) MEM_STAT_INFO) > | ^~~~ > ../../gcc/config/riscv/riscv.cc:2816:10: note: in expansion of macro > 'gen_rtx_UNSPEC' > 2816 | base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base), > | ^~~~~~~~~~~~~~ > cc1plus: all warnings being treated as errors > make[3]: *** [Makefile:2787: riscv.o] Error 1
Indeed. C++20, in particular https://wg21.link/P1120R0 paper voted into it, deprecates various operations between enumerators from different enumeration types etc., and as we've switched to -std=gnu++20 by default, this now results in warnings or errors during stage2 and onwards. The following patch should fix riscv build. Tested on x86_64 with a cross to riscv, by doing make clean; make -j32 CXXFLAGS='-g -std=gnu++20' in the gcc/ directory. Ok for trunk? 2025-11-28 Jakub Jelinek <[email protected]> * config/riscv/riscv-v.cc (expand_const_vector_onestep): Avoid bitwise ops between enumerators from different enum types. (emit_vec_cvt_x_f): Likewise. (emit_vec_cvt_x_f_rtz): Likewise. * config/riscv/riscv.cc (riscv_unspec_address_offset): Avoid arithmetics between enumerators from different enum types. --- gcc/config/riscv/riscv-v.cc.jj 2025-11-25 10:03:25.088913311 +0100 +++ gcc/config/riscv/riscv-v.cc 2025-11-28 21:08:31.370206551 +0100 @@ -1811,7 +1811,8 @@ expand_const_vector_onestep (rtx target, rtx dest = gen_reg_rtx (mode); insn_code icode = code_for_pred_mov (mode); rtx ops3[] = {dest, tmp3, tmp1}; - emit_nonvlmax_insn (icode, __MASK_OP_TUMA | UNARY_OP_P, ops3, GEN_INT (n)); + emit_nonvlmax_insn (icode, (unsigned) __MASK_OP_TUMA | UNARY_OP_P, + ops3, GEN_INT (n)); emit_move_insn (target, dest); } @@ -5265,7 +5266,7 @@ emit_vec_cvt_x_f (rtx op_dest, rtx op_sr { insn_code icode = code_for_pred_fcvt_x_f (UNSPEC_VFCVT, vec_mode); - if (type & USE_VUNDEF_MERGE_P) + if (type & (insn_type) USE_VUNDEF_MERGE_P) { rtx cvt_x_ops[] = {op_dest, mask, op_src}; emit_vlmax_insn (icode, type, cvt_x_ops); @@ -5333,7 +5334,7 @@ emit_vec_cvt_x_f_rtz (rtx op_dest, rtx o { insn_code icode = code_for_pred (FIX, vec_mode); - if (type & USE_VUNDEF_MERGE_P) + if (type & (insn_type) USE_VUNDEF_MERGE_P) { rtx cvt_x_ops[] = {op_dest, mask, op_src}; emit_vlmax_insn (icode, type, cvt_x_ops); --- gcc/config/riscv/riscv.cc.jj 2025-11-28 10:59:21.178392367 +0100 +++ gcc/config/riscv/riscv.cc 2025-11-28 21:03:40.746303717 +0100 @@ -2864,7 +2864,7 @@ riscv_unspec_address_offset (rtx base, r enum riscv_symbol_type symbol_type) { base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base), - UNSPEC_ADDRESS_FIRST + symbol_type); + UNSPEC_ADDRESS_FIRST + (int) symbol_type); if (offset != const0_rtx) base = gen_rtx_PLUS (Pmode, base, offset); return gen_rtx_CONST (Pmode, base); Jakub
