On 11/27/25 6:35 AM, Robin Dapp wrote:
For high-performance OoO uarchs, the number of ALUs is usually reflected
directly in instruction throughput. So in theory we could derive the scalar
vs vector scaling factor from the CPU scheduling model.
I looked at the GCC RISC-V scheduling models (spacemit-x60.md, xiangshan.md,
sifive-p600.md) - they do have ALU unit counts defined. I also noticed LLVM's
SchedMachineModel has similar information (throughput, latency, resource units
per instruction class). Not sure if LLVM already uses this for vector cost
scaling though.
Right now there is no way to access that information during vector costing,
unfortunately. Well, not no way at all, but it hasn't been wired up at least.
And the vector costing is coarser in that it doesn't distinguish between
individual ALU ops etc. It would be nice to establish a connection there in
the mid to long term. One question is whether the scheduler model is the right
"ground truth" choice or if there should be another unified file containing
everything.
I'd think the scheduler model would be tough to extract what we want
from, though it would likely be a lot more accurate if we could.
If there's any hook that gets us into target bits, then we could query
the issue rate as a reasonable proxy.
Jeff
