v2 pushed On Thu, Nov 27, 2025 at 9:16 AM KuanLin Chen <[email protected]> wrote:
> I'll fix it. Thanks for you remind. :-) > > Peter Bergner <[email protected]> 於 2025年11月27日週四 上午4:52寫道： > > > > On 11/25/25 11:29 PM, Kuan-Lin Chen wrote: > > > diff --git a/gcc/config/riscv/riscv-opts.h > b/gcc/config/riscv/riscv-opts.h > > > index bca5382485c..c112b1da47c 100644 > > > --- a/gcc/config/riscv/riscv-opts.h > > > +++ b/gcc/config/riscv/riscv-opts.h > > > @@ -61,6 +61,7 @@ enum riscv_microarchitecture_type { > > > generic_ooo, > > > mips_p8700, > > > tt_ascalon_d8, > > > + andes_23_series, > > > andes_25_series, > > > spacemit_x60, > > > }; > > > > [snip] > > > > > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > > > index affccec2b5e..aa4631e15a4 100644 > > > --- a/gcc/config/riscv/riscv.md > > > +++ b/gcc/config/riscv/riscv.md > > > @@ -674,7 +674,7 @@ > > > ;; Keep this in sync with enum riscv_microarchitecture. > > > (define_attr "tune" > > > > "generic,sifive_7,sifive_p400,sifive_p600,xiangshan,generic_ooo,mips_p8700, > > > - tt_ascalon_d8,andes_25_series,spacemit_x60" > > > + tt_ascalon_d8,andes_25_series,andes_23_series,spacemit_x60" > > > (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)"))) > > > > The comment above riscv_microarchitecture_type states: > > > > /* Keep this list in sync with define_attr "tune" in riscv.md. */ > > > > This means not only do they need to have the same names, but they need > > to be in the same order in both lists, which they are not in your patch. > > Otherwise, you run into the problem fixed by Jeff in commit 2b7afb69ab4 > > > > [RISC-V] Fix ordering of pipeline models > > > > ...which will result in using the wrong pipeline schedule for your cpu. > > > > Peter > > > > >
