From: Mark Zhuang <[email protected]>
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_CORE): Add xsmtvdot to
spacemit-x60
* config/riscv/riscv-ext.def: Add xsmtvdot
* config/riscv/riscv-ext.opt: Ditto
* config/riscv/t-riscv: Ditto
* doc/riscv-ext.texi: Ditto
* config/riscv/riscv-ext-spacemit.def: Define xsmtvdot
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-smt-1.c: New test.
---
gcc/config/riscv/riscv-cores.def | 2 +-
gcc/config/riscv/riscv-ext-spacemit.def | 36 +++++++++++++++++++
gcc/config/riscv/riscv-ext.def | 1 +
gcc/config/riscv/riscv-ext.opt | 5 +++
gcc/config/riscv/t-riscv | 3 +-
gcc/doc/riscv-ext.texi | 4 +++
gcc/testsuite/gcc.target/riscv/predef-smt-1.c | 14 ++++++++
7 files changed, 63 insertions(+), 2 deletions(-)
create mode 100644 gcc/config/riscv/riscv-ext-spacemit.def
create mode 100644 gcc/testsuite/gcc.target/riscv/predef-smt-1.c
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index abe9d496cda..c1c1d5daecb 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -182,7 +182,7 @@ RISCV_CORE("andes-ax25",
"rv64imafdc_zicsr_zifencei_xandesperf", "andes-25-
RISCV_CORE("andes-a27", "rv32imafdc_zicsr_zifencei_xandesperf",
"andes-25-series")
RISCV_CORE("andes-ax27", "rv64imafdc_zicsr_zifencei_xandesperf",
"andes-25-series")
RISCV_CORE("spacemit-x60", "rv64imafdcv_zba_zbb_zbc_zbs_zicboz_zicond_"
- "zbkc_zfh_zvfh_zvkt_zvl256b_sscofpmf",
+ "zbkc_zfh_zvfh_zvkt_zvl256b_sscofpmf_xsmtvdot",
"spacemit-x60")
#undef RISCV_CORE
diff --git a/gcc/config/riscv/riscv-ext-spacemit.def
b/gcc/config/riscv/riscv-ext-spacemit.def
new file mode 100644
index 00000000000..3482384e1c4
--- /dev/null
+++ b/gcc/config/riscv/riscv-ext-spacemit.def
@@ -0,0 +1,36 @@
+/* SpacemiT extension definition file for RISC-V.
+ Copyright (C) 2025 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>.
+
+Please run `make riscv-regen` in build folder to make sure updated anything.
+
+Format of DEFINE_RISCV_EXT, please refer to riscv-ext.def. */
+
+DEFINE_RISCV_EXT(
+ /* NAME */ xsmtvdot,
+ /* UPPERCASE_NAME */ XSMTVDOT,
+ /* FULL_NAME */ "SpacemiT vector dot product extension",
+ /* DESC */ "",
+ /* URL */ ,
+ /* DEP_EXTS */ ({"zve32x"}),
+ /* SUPPORTED_VERSIONS */ ({{1, 0}}),
+ /* FLAG_GROUP */ xsmt,
+ /* BITMASK_GROUP_ID */ BITMASK_NOT_YET_ALLOCATED,
+ /* BITMASK_BIT_POSITION*/ BITMASK_NOT_YET_ALLOCATED,
+ /* EXTRA_EXTENSION_FLAGS */ 0)
+
diff --git a/gcc/config/riscv/riscv-ext.def b/gcc/config/riscv/riscv-ext.def
index 80f534c6461..62d638015f3 100644
--- a/gcc/config/riscv/riscv-ext.def
+++ b/gcc/config/riscv/riscv-ext.def
@@ -2084,3 +2084,4 @@ DEFINE_RISCV_EXT(
#include "riscv-ext-ventana.def"
#include "riscv-ext-mips.def"
#include "riscv-ext-andes.def"
+#include "riscv-ext-spacemit.def"
diff --git a/gcc/config/riscv/riscv-ext.opt b/gcc/config/riscv/riscv-ext.opt
index a24f4531731..af8e556842b 100644
--- a/gcc/config/riscv/riscv-ext.opt
+++ b/gcc/config/riscv/riscv-ext.opt
@@ -55,6 +55,9 @@ int riscv_xmips_subext
TargetVariable
int riscv_xsf_subext
+TargetVariable
+int riscv_xsmt_subext
+
TargetVariable
int riscv_xthead_subext
@@ -467,3 +470,5 @@ Mask(XANDESVPACKFPH) Var(riscv_xandes_subext)
Mask(XANDESVDOT) Var(riscv_xandes_subext)
+Mask(XSMTVDOT) Var(riscv_xsmt_subext)
+
diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index 3f92feab50e..2761e5e20c0 100644
--- a/gcc/config/riscv/t-riscv
+++ b/gcc/config/riscv/t-riscv
@@ -222,7 +222,8 @@ RISCV_EXT_DEFS = \
$(srcdir)/config/riscv/riscv-ext-thead.def \
$(srcdir)/config/riscv/riscv-ext-ventana.def \
$(srcdir)/config/riscv/riscv-ext-mips.def \
- $(srcdir)/config/riscv/riscv-ext-andes.def
+ $(srcdir)/config/riscv/riscv-ext-andes.def \
+ $(srcdir)/config/riscv/riscv-ext-spacemit.def
$(srcdir)/config/riscv/riscv-ext.opt: $(RISCV_EXT_DEFS)
diff --git a/gcc/doc/riscv-ext.texi b/gcc/doc/riscv-ext.texi
index 13056e73bad..0dc667b561c 100644
--- a/gcc/doc/riscv-ext.texi
+++ b/gcc/doc/riscv-ext.texi
@@ -746,4 +746,8 @@
@tab 5.0
@tab Andes vector dot product extension
+@item xsmtvdot
+@tab 1.0
+@tab SpacemiT vector dot product extension
+
@end multitable
diff --git a/gcc/testsuite/gcc.target/riscv/predef-smt-1.c
b/gcc/testsuite/gcc.target/riscv/predef-smt-1.c
new file mode 100644
index 00000000000..4556953ed48
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-smt-1.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xsmtvdot -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xsmtvdot)
+#error "__riscv_xsmtvdot"
+#endif
+
+ return 0;
+}
--
2.34.1
