Hi All,
The following patch has been bootstrapped and regtested on powerpc64le-linux.
Recognize the pattern like below,
dst = (a & ~mask) | (b & mask);
(or equivalently (a & mask1) | (b & mask2) where mask1 == ~mask2) and implement
it with a single xxsel (VSX) or vsel (Altivec) instruction when the two masks
are constant vectors and bitwise complements.
The new define_insn_and_split matches the generic IOR-of-ANDs form and, when
rs6000_vector_complement_masks_p confirms these are bitwise complements,
replaces it with the existing altivec_vsel<mode>4 pattern which already emits
xxsel or vsel as appropriate.
2025-11-27 Jeevitha Palanisamy <[email protected]>
gcc/
PR target/119040
* config/rs6000/altivec.md (altivec_vsel_const_vector<mode>): New
splitter.
* config/rs6000/rs6000-protos.h (rs6000_vector_complement_masks_p): New
declaration.
* config/rs6000/rs6000.cc (get_def_for_reg): New helper function.
(rs6000_vector_complement_masks_p): New function to check whether two
constant vectors are bitwise complements.
gcc/testsuite/
PR target/119040
* gcc.target/powerpc/pr119040.c: New test.
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 3336b0c75dd..f722694ceaa 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -755,6 +755,25 @@ (define_insn "altivec_vsel<mode>4"
[(set_attr "type" "vecmove")
(set_attr "isa" "<VSisa>")])
+(define_insn_and_split "altivec_vsel_const_vector<mode>"
+ [(set (match_operand:VM 0 "register_operand" "=wa,v")
+ (ior:VM
+ (and:VM (match_operand:VM 1 "register_operand" "wa,v")
+ (match_operand:VM 2 "register_operand" "wa,v"))
+ (and:VM (match_operand:VM 3 "register_operand" "wa,v")
+ (match_operand:VM 4 "register_operand" "wa,v"))))]
+ "VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)
+ && rs6000_vector_complement_masks_p (operands[2],operands[4])"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+{
+ emit_insn (gen_altivec_vsel<mode>4 (operands[0], operands[1], operands[3],
operands[4]));
+ DONE;
+}
+ [(set_attr "type" "vecmove")
+ (set_attr "isa" "<VSisa>")])
+
;; Fused multiply add.
(define_insn "*altivec_fmav4sf4"
diff --git a/gcc/config/rs6000/rs6000-protos.h
b/gcc/config/rs6000/rs6000-protos.h
index 234eb0ae2b3..54454af41ce 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -160,6 +160,7 @@ extern bool rs6000_function_pcrel_p (struct function *);
extern bool rs6000_pcrel_p (void);
extern bool rs6000_fndecl_pcrel_p (const_tree);
extern void rs6000_output_addr_vec_elt (FILE *, int);
+extern bool rs6000_vector_complement_masks_p (rtx op3, rtx op4);
/* Different PowerPC instruction formats that are used by GCC. There are
various other instruction formats used by the PowerPC hardware, but these
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 1d5cd25c0f0..7166ac92860 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -28445,6 +28445,49 @@ rs6000_generate_vsigned2_code (bool signed_convert,
rtx dst, rtx src1,
emit_insn (gen_p8_vmrgew_v4si (dst, rtx_tmp2, rtx_tmp3));
}
+/* Helper to find the defining insn for a register. */
+static rtx_insn *
+get_def_for_reg (rtx reg)
+{
+ df_ref def = DF_REG_DEF_CHAIN (REGNO (reg));
+ if (!def)
+ return NULL;
+ return DF_REF_INSN (def);
+}
+
+bool
+rs6000_vector_complement_masks_p (rtx op3, rtx op4)
+{
+ if (REG_P (op3))
+ {
+ rtx_insn *def = get_def_for_reg(op3);
+ if (def && GET_CODE (PATTERN (def)) == SET)
+ op3 = SET_SRC (PATTERN (def));
+ }
+
+ if (REG_P (op4))
+ {
+ rtx_insn *def = get_def_for_reg(op4);
+ if (def && GET_CODE (PATTERN (def)) == SET)
+ op4 = SET_SRC (PATTERN (def));
+ }
+
+ if (CONST_VECTOR_P (op3) && CONST_VECTOR_P (op4))
+ {
+ for (int i = 0; i < CONST_VECTOR_NUNITS (op3); i++)
+ {
+ HOST_WIDE_INT v3 = INTVAL (CONST_VECTOR_ELT (op3, i));
+ HOST_WIDE_INT v4 = INTVAL (CONST_VECTOR_ELT (op4, i));
+
+ if ((v3 ^ v4) != -1)
+ return false;
+ }
+ return true;
+ }
+
+ return false;
+}
+
/* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
static bool
diff --git a/gcc/testsuite/gcc.target/powerpc/pr119040.c
b/gcc/testsuite/gcc.target/powerpc/pr119040.c
new file mode 100644
index 00000000000..61863e5e329
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr119040.c
@@ -0,0 +1,25 @@
+/* PR target/119040 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+/* { dg-final { scan-assembler-times "xxsel" 2 } } */
+
+#include <altivec.h>
+
+vector signed short
+select_char (vector signed short l, vector signed short r)
+{
+ vector signed short mask = {63, 63, 63, 63, 63, 63, 63, 63};
+ l = l & ~mask;
+ l |= r & mask;
+ return l;
+}
+
+vector signed int
+select_int (vector signed int l, vector signed int r)
+{
+ vector signed int mask = {63, 63, 63, 63};
+ l = l & ~mask;
+ l |= r & mask;
+ return l;
+}
+
