This patch adds support to generate xscvhpdp and xscvdphp on Power9 systems and later, to convert between _Float16 and float scalar values.
All 11 patches have been tested on little endian and big endian PowerPC servers with no regressions. Can I check in these patches? 2025-11-14 Michael Meissner <[email protected]> gcc/ * config/rs6000/float16.md (FP16_HW): New mode iterator. (extendhf<mode>2): Add support converting between HFmode and SFmode/DFmoded if we are on power9 or later. (trunc<mode>hf2): Likewise. * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define __FLOAT16_HW__ if we have hardware support for _Float16. * config/rs6000/rs6000.cc (rs6000_init_hard_regno_mode_ok): Mark that we use VSX arithmetic support for V8HFmode if we are a power9 or later. --- gcc/config/rs6000/float16.md | 22 ++++++++++++++++++++++ gcc/config/rs6000/rs6000-c.cc | 3 +++ gcc/config/rs6000/rs6000.cc | 3 +++ 3 files changed, 28 insertions(+) diff --git a/gcc/config/rs6000/float16.md b/gcc/config/rs6000/float16.md index 1e6339754b2..579703517d5 100644 --- a/gcc/config/rs6000/float16.md +++ b/gcc/config/rs6000/float16.md @@ -26,6 +26,10 @@ (define_mode_iterator FP16 [BF HF]) (define_mode_iterator VS_FP16 [BF HF V8BF V8HF]) (define_mode_iterator VFP16 [V8BF V8HF]) +;; Mode iterator for 16-bit floating point modes on machines with +;; hardware support both as a scalar and as a vector. +(define_mode_iterator FP16_HW [(HF "TARGET_FLOAT16_HW")]) + ;; Mode attribute giving the vector mode for a 16-bit floating point ;; scalar in both upper and lower case. (define_mode_attr FP16_VECTOR8 [(BF "V8BF") @@ -157,3 +161,21 @@ (define_insn "*vecdup<mode>_const" } [(set_attr "type" "veclogical,vecperm") (set_attr "prefixed" "*,yes")]) + +;; Convert IEEE 16-bit floating point to/from other floating point modes. + +(define_insn "extendhf<mode>2" + [(set (match_operand:SFDF 0 "vsx_register_operand" "=wa") + (float_extend:SFDF + (match_operand:HF 1 "vsx_register_operand" "wa")))] + "TARGET_FLOAT16_HW" + "xscvhpdp %x0,%x1" + [(set_attr "type" "fpsimple")]) + +(define_insn "trunc<mode>hf2" + [(set (match_operand:HF 0 "vsx_register_operand" "=wa") + (float_truncate:HF + (match_operand:SFDF 1 "vsx_register_operand" "wa")))] + "TARGET_FLOAT16_HW" + "xscvdphp %x0,%x1" + [(set_attr "type" "fpsimple")]) diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 70e6c6ebdc9..31a166a1c0f 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -588,6 +588,9 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) { rs6000_define_or_undefine_macro (define_p, "__FLOAT16__"); rs6000_define_or_undefine_macro (define_p, "__BFLOAT16__"); + + if ((flags & OPTION_MASK_P9_VECTOR) != 0) + rs6000_define_or_undefine_macro (define_p, "__FLOAT16_HW__"); } /* Tell the user if we are targeting CELL. */ if (rs6000_cpu == PROCESSOR_CELL) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 8004f6449ac..a913f91b6e5 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -3009,6 +3009,9 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_vector_mem[BFmode] = VECTOR_VSX; rs6000_vector_align[HFmode] = 16; rs6000_vector_align[BFmode] = 16; + + if (TARGET_P9_VECTOR) + rs6000_vector_unit[V8HFmode] = VECTOR_VSX; } /* DFmode, see if we want to use the VSX unit. Memory is handled -- 2.51.1 -- Michael Meissner, IBM PO Box 98, Ayer, Massachusetts, USA, 01432 email: [email protected]
