On Thu, Nov 13, 2025 at 7:22 AM liuhongt <[email protected]> wrote: > > For instruction sequence like > kmovb %k0, %edx > kmovb %k1, %ecx > orb %cl, %dl > je .L5 > > if only CCZ is cared, it can be optimized to > > kortestb %k1, %k0 > je .L5 > > Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32}. > Ready push to trunk. > > gcc/ChangeLog: > > * config/i386/i386.md (*ior<mode>_ccz_1): New define_insn. > > gcc/testsuite/ChangeLog: > > * gcc.target/i386/kortest_ccz-1.c: New test. > --- > gcc/config/i386/i386.md | 16 ++++++++++++++++ > gcc/testsuite/gcc.target/i386/kortest_ccz-1.c | 13 +++++++++++++ > 2 files changed, 29 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/i386/kortest_ccz-1.c > > diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md > index 3ea2439526b..ae26ef02c22 100644 > --- a/gcc/config/i386/i386.md > +++ b/gcc/config/i386/i386.md > @@ -14203,6 +14203,22 @@ (define_insn "*<code>si_2_zext_imm" > (set_attr "isa" "*,apx_ndd") > (set_attr "mode" "SI")]) > > +;; It must be put before *<code><mode>_3, the blow one. > +(define_insn "*ior<mode>_ccz_1" > + [(set (reg:CCZ FLAGS_REG) > + (compare:CCZ > + (ior:SWI1248_AVX512BWDQ_64 > + (match_operand:SWI1248_AVX512BWDQ_64 1 "nonimmediate_operand" > "%0,?k") > + (match_operand:SWI1248_AVX512BWDQ_64 2 "<general_operand>" "<g>, > k")) > + (const_int 0))) > + (clobber (match_scratch:SWI1248_AVX512BWDQ_64 0 "=<r>, k"))]
You can use 'X' constraint instead of 'k' here, so "<g>, X". The capital 'X' will signal the register allocator that no register is actually needed for output. Please see "extendsidi2_1" or "extendditi2" in i386.md for some examples. Uros.
