From: Pan Li <[email protected]>
Add asm dump check and run test for vec_duplicate + vwmaccu.vv
combine to vwmacc.vx, with the GR2VR cost is 0, 2 and 15.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Add asm check
for vwmaccu.vx.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h: Add test helper
macros.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h: Add test
data for run test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmaccu-run-1-u64.c: New test.
Signed-off-by: Pan Li <[email protected]>
---
.../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-2-u16.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-2-u32.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-2-u64.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-3-u16.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-3-u32.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-3-u64.c | 2 +
.../rvv/autovec/vx_vf/vx_vwmaccu-run-1-u64.c | 18 +++++++
.../riscv/rvv/autovec/vx_vf/vx_widen.h | 21 ++++++++
.../riscv/rvv/autovec/vx_vf/vx_widen_data.h | 54 +++++++++++++++++++
12 files changed, 111 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmaccu-run-1-u64.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index be4d23c2f43..1a48afa2788 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -11,6 +11,7 @@
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-times {vadd.vx} 2 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 2 } } */
@@ -34,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vwmulu.vx} } } */
/* { dg-final { scan-assembler-not {vwaddu.wx} } } */
/* { dg-final { scan-assembler-not {vwsubu.wx} } } */
+/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index 56dd314a7e1..2b00614d2f4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -11,6 +11,7 @@
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-times {vadd.vx} 2 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 2 } } */
@@ -34,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vwmulu.vx} } } */
/* { dg-final { scan-assembler-not {vwaddu.wx} } } */
/* { dg-final { scan-assembler-not {vwsubu.wx} } } */
+/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index 685f5f631ef..8cbf47e2eb4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -11,6 +11,7 @@
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -37,3 +38,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-times {vwmulu.vx} 1 } } */
/* { dg-final { scan-assembler-times {vwaddu.wx} 1 } } */
/* { dg-final { scan-assembler-times {vwsubu.wx} 1 } } */
+/* { dg-final { scan-assembler-times {vwmaccu.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index 391c59f502a..9aa9029d3d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -11,6 +11,7 @@
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -34,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vwmulu.vx} } } */
/* { dg-final { scan-assembler-not {vwaddu.wx} } } */
/* { dg-final { scan-assembler-not {vwsubu.wx} } } */
+/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index 2bcb6a136ff..2ffd850fa9f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -11,6 +11,7 @@
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -34,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vwmulu.vx} } } */
/* { dg-final { scan-assembler-not {vwaddu.wx} } } */
/* { dg-final { scan-assembler-not {vwsubu.wx} } } */
+/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index 0aa6a212c1e..8bb5c50413a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -11,6 +11,7 @@
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -34,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vwmulu.vx} } } */
/* { dg-final { scan-assembler-not {vwaddu.wx} } } */
/* { dg-final { scan-assembler-not {vwsubu.wx} } } */
+/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 48e095f63ff..9f5351615dd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -11,6 +11,7 @@
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -34,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vwmulu.vx} } } */
/* { dg-final { scan-assembler-not {vwaddu.wx} } } */
/* { dg-final { scan-assembler-not {vwsubu.wx} } } */
+/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index 761ce5d1a56..069efefa7fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -11,6 +11,7 @@
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -34,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vwmulu.vx} } } */
/* { dg-final { scan-assembler-not {vwaddu.wx} } } */
/* { dg-final { scan-assembler-not {vwsubu.wx} } } */
+/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 1eebec94a6d..04332ff70b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -11,6 +11,7 @@
TEST_BINARY_VX_UNSIGNED_0(T)
TEST_TERNARY_VX_UNSIGNED_0(T)
TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
+TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -34,3 +35,4 @@ TEST_WIDEN_BINARY_VX_UNSIGNED(T, NT)
/* { dg-final { scan-assembler-not {vwmulu.vx} } } */
/* { dg-final { scan-assembler-not {vwaddu.wx} } } */
/* { dg-final { scan-assembler-not {vwsubu.wx} } } */
+/* { dg-final { scan-assembler-not {vwmaccu.vx} } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmaccu-run-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmaccu-run-1-u64.c
new file mode 100644
index 00000000000..c0581415e1f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vwmaccu-run-1-u64.c
@@ -0,0 +1,18 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_widen.h"
+#include "vx_widen_data.h"
+
+#define WT uint64_t
+#define NT uint32_t
+#define NAME wmacc
+#define TEST_DATA DEF_BINARY_WIDEN_STRUCT_0_VAR_WRAP(WT, NT, NAME)
+#define DATA_TYPE DEF_BINARY_WIDEN_STRUCT_0_TYPE_WRAP(WT, NT, NAME)
+
+DEF_VX_WIDEN_TERNARY_CASE_0_WRAP(WT, NT, +, *, NAME)
+
+#define TEST_RUN(WT, NT, NAME, vd, vs2, rs1, N) \
+ RUN_VX_WIDEN_TERNARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, N)
+
+#include "vx_widen_vx_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
index 5be5f2d456e..cd73a1b5f48 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen.h
@@ -45,6 +45,24 @@ test_vx_widen_binary_##NAME##_##WT##_##NT##_case_1 (WT *
restrict vd, \
#define RUN_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, NAME, vd, vs2, rs1, n) \
RUN_VX_WIDEN_BINARY_CASE_1(WT, NT, NAME, vd, vs2, rs1, n)
+#define DEF_VX_WIDEN_TERNARY_CASE_0(WT, NT, OP1, OP2, NAME) \
+void \
+test_vx_widen_ternary_##NAME##_##WT##_##NT##_case_0 (WT * restrict vd, \
+ NT * restrict vs2, \
+ NT rs1, \
+ unsigned n) \
+{ \
+ for (unsigned i = 0; i < n; i++) \
+ vd[i] = vd[i] OP1 (WT)vs2[i] OP2 (WT)rs1; \
+}
+
+#define DEF_VX_WIDEN_TERNARY_CASE_0_WRAP(WT, NT, OP1, OP2, NAME) \
+ DEF_VX_WIDEN_TERNARY_CASE_0(WT, NT, OP1, OP2, NAME)
+#define RUN_VX_WIDEN_TERNARY_CASE_0(WT, NT, NAME, vd, vs2, rs1, n) \
+ test_vx_widen_ternary_##NAME##_##WT##_##NT##_case_0(vd, vs2, rs1, n)
+#define RUN_VX_WIDEN_TERNARY_CASE_0_WRAP(WT, NT, NAME, vd, vs2, rs1, n) \
+ RUN_VX_WIDEN_TERNARY_CASE_0(WT, NT, NAME, vd, vs2, rs1, n)
+
#define TEST_WIDEN_BINARY_VX_UNSIGNED(WT, NT) \
DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, +, add) \
DEF_VX_WIDEN_BINARY_CASE_0_WRAP(WT, NT, -, sub) \
@@ -52,4 +70,7 @@ test_vx_widen_binary_##NAME##_##WT##_##NT##_case_1 (WT *
restrict vd, \
DEF_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, +, add) \
DEF_VX_WIDEN_BINARY_CASE_1_WRAP(WT, NT, -, sub) \
+#define TEST_WIDEN_TERNARY_VX_UNSIGNED(WT, NT) \
+ DEF_VX_WIDEN_TERNARY_CASE_0_WRAP(WT, NT, +, *, wmadd)
+
#endif
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
index af7d8358ad9..9b2460f6b26 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_widen_data.h
@@ -59,6 +59,7 @@
DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, add)
DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, sub)
DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, mul)
+DEF_BINARY_WIDEN_STRUCT_0_WRAP(uint64_t, uint32_t, wmacc)
#define DEF_BINARY_WIDEN_STRUCT_1(WT, NT, NAME) \
DEF_BINARY_WIDEN_STRUCT_1_TYPE_WRAP(WT, NT, NAME) \
@@ -269,4 +270,57 @@ DEF_BINARY_WIDEN_STRUCT_1_DECL_WRAP(uint64_t, uint32_t,
sub)[] = {
},
};
+DEF_BINARY_WIDEN_STRUCT_0_DECL_WRAP(uint64_t, uint32_t, wmacc)[] = {
+ {
+ /* vs2 NT */
+ {
+ 3, 3, 3, 3,
+ 7, 7, 7, 7,
+ 9, 9, 9, 9,
+ 5, 5, 5, 5,
+ },
+ /* rs1 NT */
+ 1,
+ /* expect WT */
+ {
+ 4, 4, 4, 4,
+ 9, 9, 9, 9,
+ 17, 17, 17, 17,
+ 5, 5, 5, 5,
+ },
+ /* vd WT */
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 8, 8, 8, 8,
+ 0, 0, 0, 0,
+ },
+ },
+ {
+ /* vs2 NT */
+ {
+ 4294967295ull, 4294967295ull, 4294967295ull, 4294967295ull,
+ 4294967294ull, 4294967294ull, 4294967294ull, 4294967294ull,
+ 4294967293ull, 4294967293ull, 4294967293ull, 4294967293ull,
+ 4294967292ull, 4294967292ull, 4294967292ull, 4294967292ull,
+ },
+ /* rs1 NT */
+ 2,
+ /* expect WT */
+ {
+ 8589934591ull, 8589934591ull, 8589934591ull, 8589934591ull,
+ 8589934590ull, 8589934590ull, 8589934590ull, 8589934590ull,
+ 8589934589ull, 8589934589ull, 8589934589ull, 8589934589ull,
+ 8589934584ull, 8589934584ull, 8589934584ull, 8589934584ull,
+ },
+ /* vd WT */
+ {
+ 1, 1, 1, 1,
+ 2, 2, 2, 2,
+ 3, 3, 3, 3,
+ 0, 0, 0, 0,
+ },
+ },
+};
+
#endif
--
2.43.0
