Hi Mike,
On 23/09/25 3:32 am, Michael Meissner wrote:
> See https://gcc.gnu.org/pipermail/gcc-patches/2025-September/695920.html for
> more detail about the motavation for this set of patches.
>
> This is the first patch out of ten that provides the basic frame work
> to add a CPU option field that can be set via -mcpu=<xxx>, and to pass
> the CPU option field to helper functions much like the current ISA bits
> are passed. This patch just provides the infrastructure to add this
> CPU option support. Only power6 through power11 machines have the CPU
> option set.
>
> I have bootstraped and ran the regression tests for these patches on
> both little endian and big endian Power servers. Can I check these
> patches into the trunk?
>
> 2025-09-22 Michael Meissner <[email protected]>
>
> gcc/
>
> * config/rs6000/aix71.h (RS6000_CPU_OPTION): Define and undefine macro.
> * config/rs6000/aix72.h (RS6000_CPU_OPTION): Likewise.
> * config/rs6000/aix73.h (RS6000_CPU_OPTION): Likewise.
> * config/rs6000/default64.h (RS6000_CPU_OPTION): Likewise.
> * config/rs6000/driver-rs6000.cc (RS6000_CPU_OPTION): Likewise.
> * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Add CPU
> options parameter.
> (rs6000_cpu_cpp_builtins): Likewise.
> * config/rs6000/rs6000-cpus.def (toplevel): Add comment describing ISA
> mask bits and CPU option mask bits.
> (CPU_OPTION_POWER6_MASK): New macro.
> (CPU_OPTION_POWER7_MASK): Likewise.
> (CPU_OPTION_POWER8_MASK): Likewise.
> (CPU_OPTION_POWER9_MASK): Likewise.
> (CPU_OPTION_POWER10_MASK): Likewise.
> (CPU_OPTION_POWER11_MASK): Likewise.
> (CPU_OPTION_POWER6_ALL_MASKS): Likewise.
> (CPU_OPTION_POWER7_ALL_MASKS): Likewise.
> (CPU_OPTION_POWER8_ALL_MASKS): Likewise.
> (CPU_OPTION_POWER9_ALL_MASKS): Likewise.
> (CPU_OPTION_POWER10_ALL_MASKS): Likewise.
> (CPU_OPTION_POWER11_ALL_MASKS): Likewise.
> (power6 cpu): Switch to use RS6000_CPU_OPTION in order to set the CPU
> option mask bits.
> (power6x cpu): Likewise.
> (power7 cpu): Likewise.
> (power8): Likewise.
> (power9): Likewise.
> (power10): Likewise.
> (power11): Likewise.
> (powerpc64le): Likewise.
> * config/rs6000/rs6000-protos.h (rs6000_target_modify_macros): Add CPU
> option argument.
> (rs6000_target_modify_macros_ptr): Likewise.
> * config/rs6000/rs6000.cc (rs6000_target_modify_macros_ptr): Likewise.
> (rs6000_print_isa_options): Likewise.
> (struct rs6000_ptt): Likewise.
> (RS6000_CPU): Likewise.
> (RS6000_CPU_OPTION): Likewise.
> (DEBUG_FMT_WX): Likewise.
> (rs6000_debug_reg_global): Likewise.
> (rs6000_option_override_internal): Likewise.
> (struct rs6000_cpu_opt_mask): Likewise.
'Likewise' is incorrect here. 'New type' perhaps?
> (rs6000_cpu_opt_masks): Likewise.
'New variable' instead of 'Likewise'.
> (rs6000_pragma_target_parse): Likewise.
> (rs6000_function_specific_save): Likewise.
> (rs6000_function_specific_restore): Likewise.
> (rs6000_function_specific_print): Likewise.
> (rs6000_print_options_internal): Likewise.
Here too, 'Likewise' is incorrect.
> * config/rs6000/rs6000.opt (rs6000_cpu_option_flags): New target
> variable.
> (x_rs6000_cpu_option_flags): Likewise.
> ---
> gcc/config/rs6000/aix71.h | 2 +
> gcc/config/rs6000/aix72.h | 2 +
> gcc/config/rs6000/aix73.h | 2 +
> gcc/config/rs6000/default64.h | 2 +
> gcc/config/rs6000/driver-rs6000.cc | 2 +
> gcc/config/rs6000/rs6000-c.cc | 12 ++-
> gcc/config/rs6000/rs6000-cpus.def | 131 ++++++++++++++++++++++++-----
> gcc/config/rs6000/rs6000-protos.h | 5 +-
> gcc/config/rs6000/rs6000.cc | 129 +++++++++++++++++++++-------
> gcc/config/rs6000/rs6000.opt | 9 ++
> 10 files changed, 241 insertions(+), 55 deletions(-)
>
> diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
> index 2b21dd7cd1e..5423252f768 100644
> --- a/gcc/config/rs6000/aix71.h
> +++ b/gcc/config/rs6000/aix71.h
> @@ -133,8 +133,10 @@ do {
> \
> %{pthread: -D_THREAD_SAFE}"
>
> #define RS6000_CPU(NAME, CPU, FLAGS)
> +#define RS6000_CPU_OPTION(NAME, CPU, FLAGS, CPU_OPTION)
Instead of using CPU_OPTION, let's please make it as CPU_OPTION_FLAGS.
> #include "rs6000-cpus.def"
> #undef RS6000_CPU
> +#undef RS6000_CPU_OPTION
>
> #undef TARGET_DEFAULT
> #ifdef RS6000_BI_ARCH
> diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
> index 53c0bde5ad4..fdddc432796 100644
> --- a/gcc/config/rs6000/aix72.h
> +++ b/gcc/config/rs6000/aix72.h
> @@ -134,8 +134,10 @@ do {
> \
> %{pthread: -D_THREAD_SAFE}"
>
> #define RS6000_CPU(NAME, CPU, FLAGS)
> +#define RS6000_CPU_OPTION(NAME, CPU, FLAGS, CPU_OPTION)
> #include "rs6000-cpus.def"
> #undef RS6000_CPU
> +#undef RS6000_CPU_OPTION
>
> #undef TARGET_DEFAULT
> #ifdef RS6000_BI_ARCH
> diff --git a/gcc/config/rs6000/aix73.h b/gcc/config/rs6000/aix73.h
> index c7639368a26..37c2c081c34 100644
> --- a/gcc/config/rs6000/aix73.h
> +++ b/gcc/config/rs6000/aix73.h
> @@ -135,8 +135,10 @@ do {
> \
> %{pthread: -D_THREAD_SAFE}"
>
> #define RS6000_CPU(NAME, CPU, FLAGS)
> +#define RS6000_CPU_OPTION(NAME, CPU, FLAGS, CPU_OPTION)
> #include "rs6000-cpus.def"
> #undef RS6000_CPU
> +#undef RS6000_CPU_OPTION
>
> #undef TARGET_DEFAULT
> #ifdef RS6000_BI_ARCH
> diff --git a/gcc/config/rs6000/default64.h b/gcc/config/rs6000/default64.h
> index 7f6001ded85..d289c6dfd6d 100644
> --- a/gcc/config/rs6000/default64.h
> +++ b/gcc/config/rs6000/default64.h
> @@ -19,8 +19,10 @@ along with GCC; see the file COPYING3. If not see
> <http://www.gnu.org/licenses/>. */
>
> #define RS6000_CPU(NAME, CPU, FLAGS)
> +#define RS6000_CPU_OPTION(NAME, CPU, FLAGS, CPU_OPTION)
> #include "rs6000-cpus.def"
> #undef RS6000_CPU
> +#undef RS6000_CPU_OPTION
>
> #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
> #undef TARGET_DEFAULT
> diff --git a/gcc/config/rs6000/driver-rs6000.cc
> b/gcc/config/rs6000/driver-rs6000.cc
> index 2ab675e6d04..cacf25e9dfa 100644
> --- a/gcc/config/rs6000/driver-rs6000.cc
> +++ b/gcc/config/rs6000/driver-rs6000.cc
> @@ -45,8 +45,10 @@ along with GCC; see the file COPYING3. If not see
> static const char *rs6000_supported_cpu_names[] =
> {
> #define RS6000_CPU(NAME, CPU, FLAGS) NAME,
> +#define RS6000_CPU_OPTION(NAME, CPU, FLAGS, CPU_OPTION) NAME,
> #include "rs6000-cpus.def"
> #undef RS6000_CPU
> +#undef RS6000_CPU_OPTION
> };
>
> /* This table holds a list of cpus where their Linux AT_PLATFORM name differs
> diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc
> index d3b0a566821..823531d5e5a 100644
> --- a/gcc/config/rs6000/rs6000-c.cc
> +++ b/gcc/config/rs6000/rs6000-c.cc
> @@ -338,13 +338,16 @@ rs6000_define_or_undefine_macro (bool define_p, const
> char *name)
> #pragma GCC target, we need to adjust the macros dynamically. */
>
> void
> -rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags)
> +rs6000_target_modify_macros (bool define_p,
> + HOST_WIDE_INT flags,
> + HOST_WIDE_INT cpu_option)
> {
> if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET)
> fprintf (stderr,
> - "rs6000_target_modify_macros (%s, " HOST_WIDE_INT_PRINT_HEX ")\n",
> + "rs6000_target_modify_macros (%s, "
> + HOST_WIDE_INT_PRINT_HEX ", " HOST_WIDE_INT_PRINT_HEX ")\n",
> (define_p) ? "define" : "undef",
> - flags);
> + flags, cpu_option);
>
> /* Each of the flags mentioned below controls whether certain
> preprocessor macros will be automatically defined when
> @@ -605,7 +608,8 @@ void
> rs6000_cpu_cpp_builtins (cpp_reader *pfile)
> {
> /* Define all of the common macros. */
> - rs6000_target_modify_macros (true, rs6000_isa_flags);
> + rs6000_target_modify_macros (true, rs6000_isa_flags,
> + rs6000_cpu_option_flags);
>
> if (TARGET_FRE)
> builtin_define ("__RECIP__");
> diff --git a/gcc/config/rs6000/rs6000-cpus.def
> b/gcc/config/rs6000/rs6000-cpus.def
> index 4a1037616d7..5a9110ac5ac 100644
> --- a/gcc/config/rs6000/rs6000-cpus.def
> +++ b/gcc/config/rs6000/rs6000-cpus.def
> @@ -18,6 +18,48 @@
> along with GCC; see the file COPYING3. If not see
> <http://www.gnu.org/licenses/>. */
>
> +/* There are two different ISA/CPU options.
> +
> + Historically, the PowerPC port has used the ISA flags. These flags are
> set
> + up based on -m<options> set in rs6000.opt. There are two HOST_WIDE_INT
> + variables for these options:
> +
> + rs6000_isa_flags: These are the current named ISA options that are set
> + for the current build.
> +
> + rs6000_isa_flags_explicit: These are the current name ISA options that
> + were used by the user on the command line.
> +
> + However, the problem with the ISA bits is that you must have a named -m
> + option that the user can use on the command line. For example, the
> + -mpopcntd option sets one of the bits for ISA 2.06 features (power7), and
> + -mquad-memory-atomic sets one of the bits for ISA 2.07 features (power8).
> + In general, we don't want the user to be able to say:
> +
> + -mcpu=power9 -mno-popcntd -mno-quad-memory-atomic
> +
> + Instead there are now a parallel set of cpu option bits that are only set
> + via the -mcpu=<xxx> option. The user cannot turn these individual cpu
> + options on or off via separate -m<xxx> options.
> +
> + There are ISA options that we want the user to still turn on/off, and
> these
> + options should remain as -m<xxx> options. Some of these options that the
> + user should be able disable include:
> +
> + -mno-altivec
> + -mno-vsx
> + -mno-mma
> + -mno-crypto
> + -mno-htm
> + -mno-power8-fusion
> + -mno-power10-fusion
> +
> + There are other options historically that were documented as user -m<xxx>
> + options, and because they were documented, they need to remain as -m<xxx>
> + options at the current time. Perhaps these options can be deprecated and
> + removed in future GCC revisions. As these options are removed from GCC,
> + these options should be moved from the ISA flags to the cpu flags. */
> +
> /* ISA masks. */
> #ifndef ISA_2_1_MASKS
> #define ISA_2_1_MASKS OPTION_MASK_MFCRF
> @@ -150,7 +192,37 @@
> | OPTION_MASK_STRICT_ALIGN_OPTIONAL \
> | OPTION_MASK_VSX)
>
> -#endif
> +
> +/* CPU option mask bits that are set only via -mcpu=<xxx> options. */
> +/* CPU option mask bits that are set only via -mcpu=<xxx> options. */
Same line repeated twice.
> +#ifndef CPU_OPTION_POWER6_MASK
> +#define CPU_OPTION_POWER6_MASK (HOST_WIDE_INT_1U << 6)
> +#define CPU_OPTION_POWER7_MASK (HOST_WIDE_INT_1U << 7)
> +#define CPU_OPTION_POWER8_MASK (HOST_WIDE_INT_1U << 8)
> +#define CPU_OPTION_POWER9_MASK (HOST_WIDE_INT_1U << 9)
> +#define CPU_OPTION_POWER10_MASK (HOST_WIDE_INT_1U << 10)
> +#define CPU_OPTION_POWER11_MASK (HOST_WIDE_INT_1U << 11)
> +
> +/* Processor ISA mask bits that are set for each processor. */
> +#define CPU_OPTION_POWER6_ALL_MASKS CPU_OPTION_POWER6_MASK
> +
> +#define CPU_OPTION_POWER7_ALL_MASKS (CPU_OPTION_POWER7_MASK \
> + | CPU_OPTION_POWER6_ALL_MASKS)
> +
> +#define CPU_OPTION_POWER8_ALL_MASKS (CPU_OPTION_POWER8_MASK \
> + | CPU_OPTION_POWER7_ALL_MASKS)
> +
> +#define CPU_OPTION_POWER9_ALL_MASKS (CPU_OPTION_POWER9_MASK \
> + | CPU_OPTION_POWER8_ALL_MASKS)
> +
> +#define CPU_OPTION_POWER10_ALL_MASKS (CPU_OPTION_POWER10_MASK \
> + | CPU_OPTION_POWER9_ALL_MASKS)
> +
> +#define CPU_OPTION_POWER11_ALL_MASKS (CPU_OPTION_POWER11_MASK \
> + | CPU_OPTION_POWER10_ALL_MASKS)
> +
> +#endif /* #ifndef CPU_OPTION_POWER7_MASK. */
> +#endif /* #ifndef ISA_2_1_MASKS. */
>
> /* This table occasionally claims that a processor does not support a
> particular feature even though it does, but the feature is slower than the
> @@ -160,11 +232,15 @@
> Please keep this list in order, and don't forget to update the
> documentation
> in invoke.texi when adding a new processor or flag.
>
> - Before including this file, define a macro:
> + Before including this file, define two macros:
>
> RS6000_CPU (NAME, CPU, FLAGS)
> + RS6000_CPU_OPTION (NAME, CPU, FLAGS, CPU_OPTION)
>
> - where the arguments are the fields of struct rs6000_ptt. */
> + where the arguments of RS6000_CPU and RS6000_CPU_OPTION are the fields of
> + struct rs6000_ptt. The RS6000_CPU_OPTION's 4th argument is the CPU option
> + mask to use for this -mcpu=<xxx> variant, and it is assumed to be 0 for
> the
> + RS6000_CPU macro. */
>
> RS6000_CPU ("401", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT)
> RS6000_CPU ("403", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT |
> MASK_STRICT_ALIGN)
> @@ -234,24 +310,39 @@ RS6000_CPU ("power5", PROCESSOR_POWER5, MASK_POWERPC64
> | OPTION_MASK_PPC_GPOPT
> RS6000_CPU ("power5+", PROCESSOR_POWER5, MASK_POWERPC64 |
> OPTION_MASK_PPC_GPOPT
> | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
> | OPTION_MASK_FPRND)
> -RS6000_CPU ("power6", PROCESSOR_POWER6, MASK_POWERPC64 |
> OPTION_MASK_PPC_GPOPT
> - | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
> - | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP
> - | OPTION_MASK_RECIP_PRECISION)
> -RS6000_CPU ("power6x", PROCESSOR_POWER6, MASK_POWERPC64 |
> OPTION_MASK_PPC_GPOPT
> - | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF | OPTION_MASK_POPCNTB
> - | OPTION_MASK_FPRND | OPTION_MASK_CMPB | OPTION_MASK_DFP
> - | OPTION_MASK_RECIP_PRECISION)
> -RS6000_CPU ("power7", PROCESSOR_POWER7, MASK_POWERPC64 |
> ISA_2_6_MASKS_SERVER)
> -RS6000_CPU ("power8", PROCESSOR_POWER8, MASK_POWERPC64 | ISA_2_7_MASKS_SERVER
> - | OPTION_MASK_HTM)
> -RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 | ISA_3_0_MASKS_SERVER
> - | OPTION_MASK_HTM)
> -RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 |
> ISA_3_1_MASKS_SERVER)
> -RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 |
> POWER11_MASKS_SERVER)
> +RS6000_CPU_OPTION ("power6", PROCESSOR_POWER6,
> + MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
> + | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF
> + | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND
> + | OPTION_MASK_CMPB | OPTION_MASK_DFP
> + | OPTION_MASK_RECIP_PRECISION,
> + CPU_OPTION_POWER6_ALL_MASKS)
> +RS6000_CPU_OPTION ("power6x", PROCESSOR_POWER6,
> + MASK_POWERPC64 | OPTION_MASK_PPC_GPOPT
> + | OPTION_MASK_PPC_GFXOPT | OPTION_MASK_MFCRF
> + | OPTION_MASK_POPCNTB | OPTION_MASK_FPRND
> + | OPTION_MASK_CMPB | OPTION_MASK_DFP
> + | OPTION_MASK_RECIP_PRECISION,
> + CPU_OPTION_POWER6_ALL_MASKS)
> +RS6000_CPU_OPTION ("power7", PROCESSOR_POWER7,
> + MASK_POWERPC64 | ISA_2_6_MASKS_SERVER,
> + CPU_OPTION_POWER7_ALL_MASKS)
> +RS6000_CPU_OPTION ("power8", PROCESSOR_POWER8,
> + MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM,
> + CPU_OPTION_POWER8_ALL_MASKS)
> +RS6000_CPU_OPTION ("power9", PROCESSOR_POWER9,
> + MASK_POWERPC64 | ISA_3_0_MASKS_SERVER | OPTION_MASK_HTM,
> + CPU_OPTION_POWER9_ALL_MASKS)
> +RS6000_CPU_OPTION ("power10", PROCESSOR_POWER10,
> + MASK_POWERPC64 | ISA_3_1_MASKS_SERVER,
> + CPU_OPTION_POWER10_ALL_MASKS)
> +RS6000_CPU_OPTION ("power11", PROCESSOR_POWER11,
> + MASK_POWERPC64 | POWER11_MASKS_SERVER,
> + CPU_OPTION_POWER11_ALL_MASKS)
> RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
> RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
> | MASK_POWERPC64)
> -RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64
> - | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM)
> +RS6000_CPU_OPTION ("powerpc64le", PROCESSOR_POWER8,
> + MASK_POWERPC64 | ISA_2_7_MASKS_SERVER | OPTION_MASK_HTM,
> + CPU_OPTION_POWER8_ALL_MASKS)
> RS6000_CPU ("rs64", PROCESSOR_RS64A, OPTION_MASK_PPC_GFXOPT | MASK_POWERPC64)
> diff --git a/gcc/config/rs6000/rs6000-protos.h
> b/gcc/config/rs6000/rs6000-protos.h
> index 234eb0ae2b3..4619142d197 100644
> --- a/gcc/config/rs6000/rs6000-protos.h
> +++ b/gcc/config/rs6000/rs6000-protos.h
> @@ -324,8 +324,9 @@ extern void rs6000_cpu_cpp_builtins (struct cpp_reader *);
> extern bool rs6000_pragma_target_parse (tree, tree);
> #endif
> extern void rs6000_activate_target_options (tree new_tree);
> -extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT);
> -extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT);
> +extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT, HOST_WIDE_INT);
> +extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT,
> + HOST_WIDE_INT);
>
> #ifdef NO_DOLLAR_IN_LABEL
> const char * rs6000_xcoff_strip_dollar (const char *);
> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
> index 8dd23f8619c..a958d03b923 100644
> --- a/gcc/config/rs6000/rs6000.cc
> +++ b/gcc/config/rs6000/rs6000.cc
> @@ -276,7 +276,7 @@ bool cpu_builtin_p = false;
> /* Pointer to function (in rs6000-c.cc) that can define or undefine target
> macros that have changed. Languages that don't support the preprocessor
> don't link in rs6000-c.cc, so we can't call it directly. */
> -void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT);
> +void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
>
> /* Simplfy register classes into simpler classifications. We assume
> GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
> @@ -1169,7 +1169,7 @@ enum reg_class (*rs6000_preferred_reload_class_ptr)
> (rtx, enum reg_class)
> const int INSN_NOT_AVAILABLE = -1;
>
> static void rs6000_print_isa_options (FILE *, int, const char *,
> - HOST_WIDE_INT);
> + HOST_WIDE_INT, HOST_WIDE_INT);
> static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
>
> static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
> @@ -1792,13 +1792,17 @@ struct rs6000_ptt
> const char *const name; /* Canonical processor name. */
> const enum processor_type processor; /* Processor type enum value.
> */
> const HOST_WIDE_INT target_enable; /* Target flags to enable. */
> + const HOST_WIDE_INT cpu_option; /* CPU flags set with -mcpu=. */
> };
>
> static struct rs6000_ptt const processor_target_table[] =
> {
> -#define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
> +#define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS, 0 },
> +#define RS6000_CPU_OPTION(NAME, CPU, FLAGS, CPU_OPTION)
> \
> + { NAME, CPU, FLAGS, CPU_OPTION },
> #include "rs6000-cpus.def"
> #undef RS6000_CPU
> +#undef RS6000_CPU_OPTION
> };
>
> /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
> @@ -2220,7 +2224,8 @@ rs6000_debug_print_mode (ssize_t m)
>
> #define DEBUG_FMT_ID "%-32s= "
> #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
> -#define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
> +#define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x" \
> + ", 0x%.2" HOST_WIDE_INT_PRINT "x: "
> #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
>
> /* Print various interesting information with -mdebug=reg. */
> @@ -2400,9 +2405,11 @@ rs6000_debug_reg_global (void)
> const char *name = processor_target_table[rs6000_cpu_index].name;
> HOST_WIDE_INT flags
> = processor_target_table[rs6000_cpu_index].target_enable;
> + HOST_WIDE_INT cpu_option
> + = processor_target_table[rs6000_cpu_index].cpu_option;
>
> sprintf (flags_buffer, "-mcpu=%s flags", name);
> - rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
> + rs6000_print_isa_options (stderr, 0, flags_buffer, flags, cpu_option);
> }
> else
> fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
> @@ -2414,19 +2421,19 @@ rs6000_debug_reg_global (void)
> = processor_target_table[rs6000_tune_index].target_enable;
>
> sprintf (flags_buffer, "-mtune=%s flags", name);
> - rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
> + rs6000_print_isa_options (stderr, 0, flags_buffer, flags, 0);
We should print cpu_option here too. Any reason why we are just printing 0?
> }
> else
> fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
>
> cl_target_option_save (&cl_opts, &global_options, &global_options_set);
> rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
> - rs6000_isa_flags);
> + rs6000_isa_flags, rs6000_cpu_option_flags);
>
> rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
> - rs6000_isa_flags_explicit);
> + rs6000_isa_flags_explicit, 0);
If we have a new feature in the future power processor, say "foo", and we
want to allow the user to enable/disable this feature in gcc, then how is
"foo" represented? Will it be a part of 'target_enable'or will it be a
part of 'cpu_option' in 'struct rs6000_ptt' ? If it will be a part of
'cu_option', then we should be printing them just like we are printing
'rs6000_isa_flags_explicit'.
-Surya
