> -----Original Message-----
> From: Jiang, Haochen <[email protected]>
> Sent: Tuesday, October 21, 2025 3:32 PM
> To: [email protected]
> Cc: Liu, Hongtao <[email protected]>; [email protected]
> Subject: [PATCH] Initial Nova Lake Support
>
> Hi all,
>
> This patch will add initial support for Nova Lake according to Intel ISE.
>
> Ok for trunk?
Ok.
>
> Thx,
> Haochen
>
> gcc/ChangeLog:
>
> * common/config/i386/cpuinfo.h
> (get_intel_cpu): Handle Nova Lake.
> * common/config/i386/i386-common.cc (processor_name):
> Add Nova Lake.
> (processor_alias_table): Ditto.
> * common/config/i386/i386-cpuinfo.h (enum processor_types):
> Add INTEL_COREI7_NOVALAKE.
> * config.gcc: Add -march=novalake.
> * config/i386/driver-i386.cc (host_detect_local_cpu): Handle
> novalake.
> * config/i386/i386-c.cc (ix86_target_macros_internal): Ditto.
> * config/i386/i386-options.cc (processor_cost_table): Ditto.
> (m_NOVALAKE): New.
> (m_CORE_HYBRID): Add novalake.
> * config/i386/i386.h (enum processor_type): Ditto.
> * doc/extend.texi: Ditto.
> * doc/invoke.texi: Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * g++.target/i386/mv16.C: Ditto.
> * gcc.target/i386/funcspec-56.inc: Handle new march.
> ---
> gcc/common/config/i386/cpuinfo.h | 16 ++++++++++++++++
> gcc/common/config/i386/i386-common.cc | 3 +++
> gcc/common/config/i386/i386-cpuinfo.h | 1 +
> gcc/config.gcc | 3 ++-
> gcc/config/i386/driver-i386.cc | 6 +++++-
> gcc/config/i386/i386-c.cc | 7 +++++++
> gcc/config/i386/i386-options.cc | 4 +++-
> gcc/config/i386/i386.h | 3 +++
> gcc/doc/extend.texi | 3 +++
> gcc/doc/invoke.texi | 9 +++++++++
> gcc/testsuite/g++.target/i386/mv16.C | 6 ++++++
> gcc/testsuite/gcc.target/i386/funcspec-56.inc | 1 +
> 12 files changed, 59 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/common/config/i386/cpuinfo.h
> b/gcc/common/config/i386/cpuinfo.h
> index 9c18c04f353..dbad4a1dba6 100644
> --- a/gcc/common/config/i386/cpuinfo.h
> +++ b/gcc/common/config/i386/cpuinfo.h
> @@ -639,6 +639,22 @@ get_intel_cpu (struct __processor_model
> *cpu_model,
> default:
> break;
> }
> + /* Parse family and model for family 0x12. */
> + else if (cpu_model2->__cpu_family == 0x12)
> + switch (cpu_model2->__cpu_model)
> + {
> + case 0x01:
> + case 0x03:
> + /* Nova Lake. */
> + cpu = "novalake";
> + CHECK___builtin_cpu_is ("corei7");
> + CHECK___builtin_cpu_is ("novalake");
> + cpu_model->__cpu_type = INTEL_COREI7;
> + cpu_model->__cpu_subtype = INTEL_COREI7_NOVALAKE;
> + break;
> + default:
> + break;
> + }
> /* Parse family and model for family 0x13. */
> else if (cpu_model2->__cpu_family == 0x13)
> switch (cpu_model2->__cpu_model)
> diff --git a/gcc/common/config/i386/i386-common.cc
> b/gcc/common/config/i386/i386-common.cc
> index c71f2c13659..a447a8dd210 100644
> --- a/gcc/common/config/i386/i386-common.cc
> +++ b/gcc/common/config/i386/i386-common.cc
> @@ -2131,6 +2131,7 @@ const char *const processor_names[] =
> "arrowlake-s",
> "pantherlake",
> "diamondrapids",
> + "novalake",
> "intel",
> "lujiazui",
> "yongfeng",
> @@ -2272,6 +2273,8 @@ const pta processor_alias_table[] =
> M_CPU_SUBTYPE (INTEL_COREI7_DIAMONDRAPIDS), P_PROC_AVX10_1},
> {"wildcatlake", PROCESSOR_PANTHERLAKE, CPU_HASWELL,
> PTA_PANTHERLAKE,
> M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), P_PROC_AVX2},
> + {"novalake", PROCESSOR_NOVALAKE, CPU_HASWELL, PTA_NOVALAKE,
> + M_CPU_SUBTYPE (INTEL_COREI7_NOVALAKE), P_PROC_AVX2},
> {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
> M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
> {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL, diff --git
> a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-
> cpuinfo.h
> index 0e75626464a..e5323f10327 100644
> --- a/gcc/common/config/i386/i386-cpuinfo.h
> +++ b/gcc/common/config/i386/i386-cpuinfo.h
> @@ -106,6 +106,7 @@ enum processor_subtypes
> AMDFAM1AH_ZNVER5,
> ZHAOXIN_FAM7H_SHIJIDADAO,
> INTEL_COREI7_DIAMONDRAPIDS,
> + INTEL_COREI7_NOVALAKE,
> CPU_SUBTYPE_MAX
> };
>
> diff --git a/gcc/config.gcc b/gcc/config.gcc index 2ecce1c4e3e..8107c8dbaae
> 100644
> --- a/gcc/config.gcc
> +++ b/gcc/config.gcc
> @@ -729,7 +729,8 @@ skylake goldmont goldmont-plus tremont cascadelake
> tigerlake cooperlake \ sapphirerapids alderlake rocketlake eden-x2 nano
> nano-1000 nano-2000 nano-3000 \
> nano-x2 eden-x4 nano-x4 lujiazui yongfeng shijidadao x86-64 x86-64-v2 \
> x86-64-v3 x86-64-v4 sierraforest graniterapids graniterapids-d grandridge \ -
> arrowlake arrowlake-s clearwaterforest pantherlake diamondrapids native"
> +arrowlake arrowlake-s clearwaterforest pantherlake diamondrapids
> +novalake \ native"
>
> # Additional x86 processors supported by --with-cpu=. Each processor #
> MUST be separated by exactly one space.
> diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc
> index
> 3eacc2cbc39..d3f1210f767 100644
> --- a/gcc/config/i386/driver-i386.cc
> +++ b/gcc/config/i386/driver-i386.cc
> @@ -553,6 +553,7 @@ const char *host_detect_local_cpu (int argc, const char
> **argv)
> processor = PROCESSOR_PENTIUM;
> break;
> case 6:
> + case 18:
> case 19:
> processor = PROCESSOR_PENTIUMPRO;
> break;
> @@ -639,8 +640,11 @@ const char *host_detect_local_cpu (int argc, const
> char **argv)
> }
> else if (has_feature (FEATURE_AVX))
> {
> + /* Assume Nova Lake. */
> + if (has_feature (FEATURE_MOVRS))
> + cpu = "novalake";
> /* Assume Clearwater Forest. */
> - if (has_feature (FEATURE_USER_MSR))
> + else if (has_feature (FEATURE_USER_MSR))
> cpu = "clearwaterforest";
> else if (has_feature (FEATURE_SM3))
> {
> diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index
> 00374653c3c..2d92cee458c 100644
> --- a/gcc/config/i386/i386-c.cc
> +++ b/gcc/config/i386/i386-c.cc
> @@ -295,6 +295,10 @@ ix86_target_macros_internal (HOST_WIDE_INT
> isa_flag,
> def_or_undef (parse_in, "__diamondrapids");
> def_or_undef (parse_in, "__diamondrapids__");
> break;
> + case PROCESSOR_NOVALAKE:
> + def_or_undef (parse_in, "__novalake");
> + def_or_undef (parse_in, "__novalake__");
> + break;
>
> /* use PROCESSOR_max to not set/unset the arch macro. */
> case PROCESSOR_max:
> @@ -498,6 +502,9 @@ ix86_target_macros_internal (HOST_WIDE_INT
> isa_flag,
> case PROCESSOR_DIAMONDRAPIDS:
> def_or_undef (parse_in, "__tune_diamondrapids__");
> break;
> + case PROCESSOR_NOVALAKE:
> + def_or_undef (parse_in, "__tune_novalake__");
> + break;
> case PROCESSOR_INTEL:
> case PROCESSOR_GENERIC:
> break;
> diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
> index 35cba3fc48d..dadcf7664c6 100644
> --- a/gcc/config/i386/i386-options.cc
> +++ b/gcc/config/i386/i386-options.cc
> @@ -132,6 +132,7 @@ along with GCC; see the file COPYING3. If not see
> #define m_ARROWLAKE_S (HOST_WIDE_INT_1U<<PROCESSOR_ARROWLAKE_S)
> #define m_PANTHERLAKE (HOST_WIDE_INT_1U<<PROCESSOR_PANTHERLAKE)
> #define m_DIAMONDRAPIDS
> (HOST_WIDE_INT_1U<<PROCESSOR_DIAMONDRAPIDS)
> +#define m_NOVALAKE (HOST_WIDE_INT_1U<<PROCESSOR_NOVALAKE)
> #define m_CORE_AVX512 (m_SKYLAKE_AVX512 | m_CANNONLAKE \
> | m_ICELAKE_CLIENT | m_ICELAKE_SERVER |
> m_CASCADELAKE \
> | m_TIGERLAKE | m_COOPERLAKE | m_SAPPHIRERAPIDS \
> @@ -140,7 +141,7 @@ along with GCC; see the file COPYING3. If not see
> #define m_CORE_AVX2 (m_HASWELL | m_SKYLAKE | m_CORE_AVX512)
> #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE |
> m_CORE_AVX2) #define m_CORE_HYBRID (m_ALDERLAKE | m_ARROWLAKE |
> m_ARROWLAKE_S \
> - | m_PANTHERLAKE)
> + | m_PANTHERLAKE | m_NOVALAKE)
> #define m_GOLDMONT (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT)
> #define m_GOLDMONT_PLUS
> (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT_PLUS)
> #define m_TREMONT (HOST_WIDE_INT_1U<<PROCESSOR_TREMONT)
> @@ -790,6 +791,7 @@ static const struct processor_costs
> *processor_cost_table[] =
> &alderlake_cost, /* PROCESSOR_ARROWLAKE_S. */
> &alderlake_cost, /* PROCESSOR_PANTHERLAKE. */
> &icelake_cost, /* PROCESSOR_DIAMONDRAPIDS. */
> + &alderlake_cost, /* PROCESSOR_NOVALAKE. */
> &alderlake_cost, /* PROCESSOR_INTEL. */
> &lujiazui_cost, /* PROCESSOR_LUJIAZUI. */
> &yongfeng_cost, /* PROCESSOR_YONGFENG. */
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index
> 3a66d78a07c..e5ba1a40005 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -2356,6 +2356,7 @@ enum processor_type
> PROCESSOR_ARROWLAKE_S,
> PROCESSOR_PANTHERLAKE,
> PROCESSOR_DIAMONDRAPIDS,
> + PROCESSOR_NOVALAKE,
> PROCESSOR_INTEL,
> PROCESSOR_LUJIAZUI,
> PROCESSOR_YONGFENG,
> @@ -2487,6 +2488,8 @@ constexpr wide_int_bitmask PTA_DIAMONDRAPIDS =
> PTA_GRANITERAPIDS_D
> | PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_AVX10_2
> | PTA_APX_F | PTA_AMX_AVX512 | PTA_AMX_FP8 | PTA_AMX_TF32 |
> PTA_MOVRS
> | PTA_AMX_MOVRS;
> +constexpr wide_int_bitmask PTA_NOVALAKE = PTA_PANTHERLAKE |
> +PTA_PREFETCHI
> + | PTA_MOVRS;
>
> constexpr wide_int_bitmask PTA_BDVER1 = PTA_64BIT | PTA_MMX | PTA_SSE
> | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_POPCNT | PTA_LZCNT
> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index
> 94b76b75565..fb117f59665 100644
> --- a/gcc/doc/extend.texi
> +++ b/gcc/doc/extend.texi
> @@ -28408,6 +28408,9 @@ Intel Core i7 Panther Lake CPU.
> @item diamondrapids
> Intel Core i7 Diamond Rapids CPU.
>
> +@item novalake
> +Intel Core i7 Nova Lake CPU.
> +
> @item bonnell
> Intel Atom Bonnell CPU.
>
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index
> 189b2662012..3ab053e26a4 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -35170,6 +35170,15 @@ LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ,
> SERIALIZE, HRESET, AVX-VNNI, UINTR, AVXIFMA, AVXVNNIINT8,
> AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3 and
> SM4 instruction set support.
>
> +@item novalake
> +Intel Nova Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> +SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND,
> +XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX,
> +GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, WAITPKG, ADCX, AVX, AVX2, BMI,
> +BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE,
> +HRESET, KL, WIDEKL, AVX-VNNI, UINTR, AVXIFMA, AVXVNNIINT8,
> +AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4,
> USER_MSR, and MOVRS instruction set support.
> +
> @item sapphirerapids
> @itemx emeraldrapids
> Intel Sapphire Rapids/Emerald Rapids CPU with 64-bit extensions, MMX, SSE,
> diff --git a/gcc/testsuite/g++.target/i386/mv16.C
> b/gcc/testsuite/g++.target/i386/mv16.C
> index 75198f54ab9..87126a058db 100644
> --- a/gcc/testsuite/g++.target/i386/mv16.C
> +++ b/gcc/testsuite/g++.target/i386/mv16.C
> @@ -128,6 +128,10 @@ int __attribute__ ((target("arch=diamondrapids")))
> foo () {
> return 33;
> }
>
> +int __attribute__ ((target("arch=novalake"))) foo () {
> + return 34;
> +}
> +
> int main ()
> {
> int val = foo ();
> @@ -184,6 +188,8 @@ int main ()
> assert (val == 32);
> else if (__builtin_cpu_is ("diamondrapids"))
> assert (val == 33);
> + else if (__builtin_cpu_is ("novalake"))
> + assert (val == 34);
> else
> assert (val == 0);
>
> diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
> b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
> index 3d9af7acec6..f56b344b6c8 100644
> --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
> +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
> @@ -217,6 +217,7 @@ extern void test_arch_arrowlake (void)
> __attribute__((__target__("arch=arrowlak
> extern void test_arch_arrowlake_s (void)
> __attribute__((__target__("arch=arrowlake-s")));
> extern void test_arch_pantherlake (void)
> __attribute__((__target__("arch=pantherlake")));
> extern void test_arch_diamondrapids (void)
> __attribute__((__target__("arch=diamondrapids")));
> +extern void test_arch_novalake (void)
> __attribute__((__target__("arch=novalake")));
> extern void test_arch_lujiazui (void)
> __attribute__((__target__("arch=lujiazui")));
> extern void test_arch_yongfeng (void)
> __attribute__((__target__("arch=yongfeng")));
> extern void test_arch_shijidadao (void)
> __attribute__((__target__("arch=shijidadao")));
> --
> 2.31.1
