Kyrylo Tkachov <[email protected]> writes:
>> diff --git a/gcc/config/aarch64/aarch64-sve2.md
>> b/gcc/config/aarch64/aarch64-sve2.md
>> index a3cbbce8b31..d82dc41df3e 100644
>> --- a/gcc/config/aarch64/aarch64-sve2.md
>> +++ b/gcc/config/aarch64/aarch64-sve2.md
>> @@ -1124,6 +1124,42 @@
>> [(set_attr "movprfx" "yes")]
>> )
>>
>> +;; Predicated binary operations with no reverse form, merging with
>> +;; the second input.
>> +(define_insn_and_rewrite "*cond_<sve_int_op><mode>_3"
>> + [(set (match_operand:SVE_FULL_I 0 "register_operand")
>> + (unspec:SVE_FULL_I
>> + [(match_operand:<VPRED> 1 "register_operand")
>> + (unspec:SVE_FULL_I
>> + [(match_operand 5)
>> + (unspec:SVE_FULL_I
>> + [(match_operand:SVE_FULL_I 2 "register_operand")
>> + (match_operand:SVE_FULL_I 3 "register_operand")]
>> + SVE2_COND_INT_BINARY_NOREV)]
>> + UNSPEC_PRED_X)
>> + (match_operand:SVE_FULL_I 4 "register_operand")]
>> + UNSPEC_SEL))]
>> + "TARGET_SVE2
>
>
> The define_insn-related constructs should really have constraints for the
> operands.
> I know they will be likely be split before reload when it matters, but
> it’s not impossible that they can reach RA, and so the pattern should
> have information for which constraints to use.
Also, this is a define_insn_and_rewrite, so any "split" is from this
define_insn to itself. Once the define_insn is matched, it will be used
by the RA in some form.
(For avoidance of doubt, operand 5 can stay as-is. Only the
register_operands need constraints.)
Thanks,
Richard
> Ok with constraints added to the operands.
> Sorry for the long delay.
> Thanks,
> Kyrill
>
>> + && rtx_equal_p (operands[3], operands[4])"
>> + "#"
>> + "&& 1"
>> + {
>> + if (reload_completed
>> + && register_operand (operands[4], <MODE>mode)
>> + && !rtx_equal_p (operands[0], operands[4]))
>> + {
>> + emit_insn (gen_vcond_mask_<mode><vpred> (operands[0], operands[2],
>> + operands[4], operands[1]));
>> + operands[4] = operands[2] = operands[0];
>> + }
>> + else if (!CONSTANT_P (operands[5]))
>> + operands[5] = CONSTM1_RTX (<VPRED>mode);
>> + else
>> + FAIL;
>> + }
>> + [(set_attr "movprfx" "yes")]
>> +)
>> +
>> ;; Predicated binary operations with no reverse form, merging with zero.
>> ;; At present we don't generate these patterns via a cond_* optab,
>> ;; so there's no correctness requirement to handle merging with an
>> diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c
>> b/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c
>> new file mode 100644
>> index 00000000000..dbfa613649d
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c
>> @@ -0,0 +1,31 @@
>> +/* PR target/121599. */
>> +/* { dg-do compile } */
>> +/* { dg-options "-O2" } */
>> +/* { dg-final { check-function-bodies "**" "" "" } } */
>> +
>> +#include <arm_sve.h>
>> +
>> +/*
>> +** foo:
>> +** movi d([0-9]+), #0
>> +** sel z0\.b, p0, z0\.b, z\1\.b
>> +** usqadd z0\.b, p0/m, z0\.b, z\1\.b
>> +** ret
>> +*/
>> +svuint8_t foo (svbool_t pg, svuint8_t op1)
>> +{
>> + return svsqadd_u8_z (pg, op1, svdup_s8 (0));
>> +}
>> +
>> +/*
>> +** bar:
>> +** movi d([0-9]+), #0
>> +** sel z0\.b, p0, z0\.b, z\1\.b
>> +** suqadd z0\.b, p0/m, z0\.b, z\1\.b
>> +** ret
>> +*/
>> +svint8_t bar (svbool_t pg, svint8_t op1)
>> +{
>> + return svuqadd_n_s8_z (pg, op1, 0);
>> +}
>> +
>> --
>> 2.34.1
>>>
>>> Thanks,
>>> Kyrill
>>>
>>>> diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c
>>>> b/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c
>>>> new file mode 100644
>>>> index 00000000000..cd80ef9115c
>>>> --- /dev/null
>>>> +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pr121599.c
>>>> @@ -0,0 +1,31 @@
>>>> +/* PR target/121599. */
>>>> +/* { dg-do compile } */
>>>> +/* { dg-options "-O2" } */
>>>> +/* { dg-final { check-function-bodies "**" "" "" } } */
>>>> +
>>>> +#include <arm_sve.h>
>>>> +
>>>> +/*
>>>> +** foo:
>>>> +** movi d([0-9]+), #0
>>>> +** movprfx z0\.b, p0/z, z0\.b
>>>> +** usqadd z0\.b, p0/m, z0\.b, z\1\.b
>>>> +** ret
>>>> +*/
>>>> +svuint8_t foo (svbool_t pg, svuint8_t op1)
>>>> +{
>>>> + return svsqadd_u8_z (pg, op1, svdup_s8 (0));
>>>> +}
>>>> +
>>>> +/*
>>>> +** bar:
>>>> +** movi d([0-9]+), #0
>>>> +** movprfx z0\.b, p0/z, z0\.b
>>>> +** suqadd z0\.b, p0/m, z0\.b, z\1\.b
>>>> +** ret
>>>> +*/
>>>> +svint8_t bar (svbool_t pg, svint8_t op1)
>>>> +{
>>>> + return svuqadd_n_s8_z (pg, op1, 0);
>>>> +}
>>>> +
>>>> --
>>>> 2.34.1
