> The vwsll.vi of zvbb ext take zero extend before ashift. But > we can still do some combine based on sign extend if and only > if the shift is imm and the sign extend bits are all shifted. > For example as below
I'm not sure we should go ahead with that. It feels like we're working around the vector pattern recognition using the "wrong" type and I'd rather correct that or something related to it. Maybe there is still a need for this even after changing the pattern recognition (or directly allowing widening plus/minus/...). I'm experimenting with the widening IFNs currently, can we defer until I come to a conclusion there? As it has been posted now we can still easily go for it after stage1 if needed. -- Regards Robin
