We can handle bitwise-operation reductions and reductions on mask
vectors just fine.
Bootstrapped and tested on x86_64-unknown-linux-gnu. This doesn't
fix the testcase in the PR, there's a pattern recog issue left.
PR tree-optimization/122110
* tree-vect-loop.cc (vectorizable_reduction): Relax restriction
to mode-precision operations.
---
gcc/tree-vect-loop.cc | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc
index 18360375e29..1d549e4a03e 100644
--- a/gcc/tree-vect-loop.cc
+++ b/gcc/tree-vect-loop.cc
@@ -7187,7 +7187,11 @@ vectorizable_reduction (loop_vec_info loop_vinfo,
return false;
/* Do not try to vectorize bit-precision reductions. */
- if (!type_has_mode_precision_p (op.type))
+ if (!VECTOR_BOOLEAN_TYPE_P (vectype_out)
+ && !type_has_mode_precision_p (op.type)
+ && op.code != BIT_AND_EXPR
+ && op.code != BIT_IOR_EXPR
+ && op.code != BIT_XOR_EXPR)
return false;
/* Lane-reducing ops also never can be used in a SLP reduction group
--
2.43.0
