[PATCH v2 2/4] MIPS: Add support for Allegrex min/max instructions

[David Guillen Fandos]

gcc/ChangeLog:

        * config/mips/mips.h (ISA_HAS_MIN_MAX): Defined a new macro.
        * config/mips/mips.md (sminsi3): Defined a new instruction.
        (smaxsi3): Defined a new instruction.

gcc/testsuite/ChangeLog:

        * gcc.target/mips/max-1.c: New test.
        * gcc.target/mips/min-1.c: New test.

Signed-off-by: David Guillen Fandos <da...@davidgf.net>
---
 gcc/config/mips/mips.h                |  3 +++
 gcc/config/mips/mips.md               | 21 +++++++++++++++++++++
 gcc/testsuite/gcc.target/mips/max-1.c |  9 +++++++++
 gcc/testsuite/gcc.target/mips/min-1.c |  9 +++++++++
 4 files changed, 42 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/mips/max-1.c
 create mode 100644 gcc/testsuite/gcc.target/mips/min-1.c

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 5b224b7ae0e..59225aa01d6 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1255,6 +1255,9 @@ struct mips_cpu_info {
                                  || TARGET_SMARTMIPS)                  \
                                 && !TARGET_MIPS16)
 
+/* ISA has the "min" and "max" instructions (signed min/max). */
+#define ISA_HAS_MIN_MAX                (TARGET_ALLEGREX)
+
 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
    64-bit targets also provide DSBH and DSHD.  */
 #define ISA_HAS_WSBH           ((mips_isa_rev >= 2 && !TARGET_MIPS16)  \
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 4b497c5ed7a..c6b0f20b19b 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -7629,6 +7629,27 @@
   DONE;
 })
 
+;; Min and max.
+
+(define_insn "sminsi3"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+        (smin:SI (match_operand:SI 1 "register_operand" "d")
+                 (match_operand:SI 2 "register_operand" "d")))]
+  "ISA_HAS_MIN_MAX"
+  "min\t%0,%1,%2"
+  [(set_attr "type"    "arith")
+   (set_attr "mode"    "SI")])
+
+(define_insn "smaxsi3"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+        (smax:SI (match_operand:SI 1 "register_operand" "d")
+                 (match_operand:SI 2 "register_operand" "d")))]
+  "ISA_HAS_MIN_MAX"
+  "max\t%0,%1,%2"
+  [(set_attr "type"    "arith")
+   (set_attr "mode"    "SI")])
+
+
 (define_expand "speculation_barrier"
   [(unspec_volatile [(const_int 0)] VUNSPEC_SPECULATION_BARRIER)]
   ""
diff --git a/gcc/testsuite/gcc.target/mips/max-1.c 
b/gcc/testsuite/gcc.target/mips/max-1.c
new file mode 100644
index 00000000000..f3589fc0113
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/max-1.c
@@ -0,0 +1,9 @@
+/* { dg-options "-march=allegrex" } */
+
+NOMIPS16 int
+foo_max (int a, int b)
+{
+  return (a > b) ?  a : b;
+}
+
+/* { dg-final { scan-assembler "\tmax\t" } } */
diff --git a/gcc/testsuite/gcc.target/mips/min-1.c 
b/gcc/testsuite/gcc.target/mips/min-1.c
new file mode 100644
index 00000000000..06b5e91aca9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/min-1.c
@@ -0,0 +1,9 @@
+/* { dg-options "-march=allegrex" } */
+
+NOMIPS16 int
+foo_min (int a, int b)
+{
+  return (a < b) ?  a : b;
+}
+
+/* { dg-final { scan-assembler "\tmin\t" } } */
-- 
2.50.1