From: Pan Li <[email protected]>
This patch would like to try to match the the unsigned
SAT_MUL form 5, aka below:
#define DEF_SAT_U_MUL_FMT_5(NT, WT) \
NT __attribute__((noinline)) \
sat_u_mul_##NT##_from_##WT##_fmt_5 (NT a, NT b) \
{ \
WT x = (WT)a * (WT)b; \
NT hi = x >> (sizeof(NT) * 8); \
NT lo = (NT)x; \
return lo | -!!hi; \
}
The NT is uint8_t, uint16_t, uint32_t, while the WT
is uint16_t, uint32_t and uint64_t.
20 ??? _35 = (unsigned long) a_8(D);
21 ??? _34 = (unsigned long) b_9(D);
22 ??? x_10 = _35 * _34;
23 ??? _3 = x_10 >> 8;
24 ??? hi_11 = (uint8_t) _3;
25 ??? _4 = hi_11 != 0;
26 ??? _14 = (signed char) _4;
27 ??? _5 = -_14;
28 ??? lo.0_6 = (signed char) x_10;
29 ??? _7 = _5 | lo.0_6;
30 ??? _12 = (uint8_t) _7;
31 ??? return _12;
After this series if backend implemented usmul, we have:
9 ??? <bb 2> [local count: 1073741824]:
10 ??? _12 = .SAT_MUL (b_9(D), a_8(D)); [tail call]
11 ??? return _12;
The below test suites are passed for this patch:
1. The rv64gcv fully regression tests.
2. The x86 bootstrap tests.
3. The x86 fully regression tests.
Pan Li (2):
Match: Add form 5 of unsigned SAT_MUL for mul
RISC-V: Add test case of unsigned scalar SAT_MUL form 5 for mul
gcc/match.pd | 55 ++++++++++---------
.../riscv/sat/sat_u_mul-6-u16-from-u32.c | 11 ++++
.../riscv/sat/sat_u_mul-6-u16-from-u64.rv32.c | 11 ++++
.../riscv/sat/sat_u_mul-6-u16-from-u64.rv64.c | 11 ++++
.../riscv/sat/sat_u_mul-6-u32-from-u64.rv32.c | 11 ++++
.../riscv/sat/sat_u_mul-6-u32-from-u64.rv64.c | 11 ++++
.../riscv/sat/sat_u_mul-6-u8-from-u16.c | 11 ++++
.../riscv/sat/sat_u_mul-6-u8-from-u32.c | 11 ++++
.../riscv/sat/sat_u_mul-6-u8-from-u64.rv32.c | 11 ++++
.../riscv/sat/sat_u_mul-6-u8-from-u64.rv64.c | 11 ++++
.../riscv/sat/sat_u_mul-run-6-u16-from-u32.c | 16 ++++++
.../riscv/sat/sat_u_mul-run-6-u16-from-u64.c | 16 ++++++
.../riscv/sat/sat_u_mul-run-6-u32-from-u64.c | 16 ++++++
.../riscv/sat/sat_u_mul-run-6-u8-from-u16.c | 16 ++++++
.../riscv/sat/sat_u_mul-run-6-u8-from-u32.c | 16 ++++++
.../riscv/sat/sat_u_mul-run-6-u8-from-u64.c | 16 ++++++
16 files changed, 225 insertions(+), 25 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u16-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u16-from-u64.rv32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u16-from-u64.rv64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u32-from-u64.rv32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u32-from-u64.rv64.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u8-from-u16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u8-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u8-from-u64.rv32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-6-u8-from-u64.rv64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u16-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u16-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u32-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u8-from-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u8-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-6-u8-from-u64.c
--
2.43.0
