> -----Original Message-----
> From: Wilco Dijkstra <wilco.dijks...@arm.com>
> Sent: Wednesday, September 10, 2025 5:25 PM
> To: Tamar Christina <tamar.christ...@arm.com>; GCC Patches <gcc-
> patc...@gcc.gnu.org>
> Cc: Kyrylo Tkachov <ktkac...@nvidia.com>; Alex Coplan
> <alex.cop...@arm.com>; Andrew Pinski <pins...@gmail.com>; Alice Carlotti
> <alice.carlo...@arm.com>
> Subject: Re: [PATCH] AArch64: Add isfinite expander [PR 66462]
>
> Hi Tamar,
>
> > +(define_expand "isfinite<mode>2"
> > + [(match_operand:SI 0 "register_operand")
> > + (match_operand:GPF 1 "register_operand")]
> > + "TARGET_FLOAT"
> > +{
> > + rtx op = lowpart_subreg (<V_INT_EQUIV>mode, operands[1], <MODE>mode);
>
> > Also needs force_lowpart_subreg
>
> True.
>
> > + rtx tmp = gen_reg_rtx (<V_INT_EQUIV>mode);
> > + emit_move_insn (tmp, GEN_INT (HOST_WIDE_INT_M1U << (<mantissa_bits> +
> > 1)));
> > + rtx cc_reg = gen_rtx_REG (CC_SWPmode, CC_REGNUM);
> > + emit_insn (gen_cmp_swp_lsl_reg<v_int_equiv> (op, GEN_INT (1), tmp));
> > + rtx cmp = gen_rtx_fmt_ee (LTU, SImode, cc_reg, const0_rtx);
> > + emit_insn (gen_aarch64_cstoresi (operands[0], cmp, cc_reg));
> > + DONE;
> > +}
> > +)
> > +
>
> > Hmm this looks the same as isinf except for the operator in the compare.
> > Could we combine the two patterns?
>
> Not easily since we need different conditions for eg. isnan. What could be
> abstracted perhaps is the code to create the cstoresi since that appears a bit
> convoluted.
It's fine. The patch is OK with the change above to force_lowpart_subreg.
Thanks,
Tamar
>
> Cheers,
> Wilco
