Hi Mike,
On 24/07/25 12:47 am, Michael Meissner wrote:
> diff --git a/gcc/config/rs6000/rs6000-cpus.def
> b/gcc/config/rs6000/rs6000-cpus.def
> index 4a1037616d7..df833e3d54b 100644
> --- a/gcc/config/rs6000/rs6000-cpus.def
> +++ b/gcc/config/rs6000/rs6000-cpus.def
> @@ -83,6 +83,8 @@
> #define POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
> | OPTION_MASK_POWER11)
>
> +#define FUTURE_MASKS_SERVER POWER11_MASKS_SERVER
> +
> /* Flags that need to be turned off if -mno-vsx. */
> #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX
> \
> | OPTION_MASK_FLOAT128_KEYWORD \
> @@ -160,11 +162,21 @@
> Please keep this list in order, and don't forget to update the
> documentation
> in invoke.texi when adding a new processor or flag.
>
> - Before including this file, define a macro:
> + Before including this file, define two macros:
>
> RS6000_CPU (NAME, CPU, FLAGS)
> + RS6000_CPU_ISA (NAME, CPU, FLAGS, CPU_ISA)
> +
> + where the arguments are the fields of struct rs6000_ptt.
> +
> + If RS6000_CPU_ISA is not defined, it will default to using RS6000_CPU and
> + ignoring the CPU_ISA argument. RS6000_CPU_ISA is used to define CPU ISA
> + bits that do not have an option associated with them. */>
> - where the arguments are the fields of struct rs6000_ptt. */
> +#ifndef RS6000_CPU_ISA
> +#define RS6000_CPU_ISA(NAME, CPU, FLAGS, CPU_ISA) \
> + RS6000_CPU(NAME, CPU, FLAGS)
> +#endif
Duplicate definition. This has been defined in rs6000.cc too.
>
> RS6000_CPU ("401", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT)
> RS6000_CPU ("403", PROCESSOR_PPC403, OPTION_MASK_SOFT_FLOAT |
> MASK_STRICT_ALIGN)
> @@ -249,6 +261,14 @@ RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64 |
> ISA_3_0_MASKS_SERVER
> | OPTION_MASK_HTM)
> RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 |
> ISA_3_1_MASKS_SERVER)
> RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 |
> POWER11_MASKS_SERVER)
> +
> +/* Do not define a PROCESSOR_FUTURE processor type at the current time. It
> is
> + expected that we may eventually add tuning support for a potential future
> + processor that differs from power11 support. */
> +RS6000_CPU_ISA ("future", PROCESSOR_FUTURE,
> + MASK_POWERPC64 | FUTURE_MASKS_SERVER,
> + CPU_ISA_MASK_FUTURE)
> +
> RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
> RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
> | MASK_POWERPC64)
> diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
> index c31d2975f04..6e6cb892eb1 100644
> --- a/gcc/config/rs6000/rs6000-opts.h
> +++ b/gcc/config/rs6000/rs6000-opts.h
> @@ -71,6 +71,10 @@ enum processor_type
> PROCESSOR_TITAN
> };
>
> +/* At the current time, we do not have a separate FUTURE processor. Map
> FUTURE
> + to POWER11 until we have tuning changes for the potential future
> + processor. */
> +#define PROCESSOR_FUTURE PROCESSOR_POWER11
>
> /* Types of costly dependences. */
> enum rs6000_dependence_cost
> diff --git a/gcc/config/rs6000/rs6000-protos.h
> b/gcc/config/rs6000/rs6000-protos.h
> index 234eb0ae2b3..4619142d197 100644
> --- a/gcc/config/rs6000/rs6000-protos.h
> +++ b/gcc/config/rs6000/rs6000-protos.h
> @@ -324,8 +324,9 @@ extern void rs6000_cpu_cpp_builtins (struct cpp_reader *);
> extern bool rs6000_pragma_target_parse (tree, tree);
> #endif
> extern void rs6000_activate_target_options (tree new_tree);
> -extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT);
> -extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT);
> +extern void rs6000_target_modify_macros (bool, HOST_WIDE_INT, HOST_WIDE_INT);
> +extern void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT,
> + HOST_WIDE_INT);
>
> #ifdef NO_DOLLAR_IN_LABEL
> const char * rs6000_xcoff_strip_dollar (const char *);
> diff --git a/gcc/config/rs6000/rs6000-tables.opt
> b/gcc/config/rs6000/rs6000-tables.opt
> index f5bbed5ea74..518324e7aea 100644
> --- a/gcc/config/rs6000/rs6000-tables.opt
> +++ b/gcc/config/rs6000/rs6000-tables.opt
> @@ -189,14 +189,17 @@ EnumValue
> Enum(rs6000_cpu_opt_value) String(power11) Value(53)
>
> EnumValue
> -Enum(rs6000_cpu_opt_value) String(powerpc) Value(54)
> +Enum(rs6000_cpu_opt_value) String(future) Value(54)
>
> EnumValue
> -Enum(rs6000_cpu_opt_value) String(powerpc64) Value(55)
> +Enum(rs6000_cpu_opt_value) String(powerpc) Value(55)
>
> EnumValue
> -Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(56)
> +Enum(rs6000_cpu_opt_value) String(powerpc64) Value(56)
>
> EnumValue
> -Enum(rs6000_cpu_opt_value) String(rs64) Value(57)
> +Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(57)
> +
> +EnumValue
> +Enum(rs6000_cpu_opt_value) String(rs64) Value(58)
>
> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
> index 7ee26e52b13..8b8f5c733c8 100644
> --- a/gcc/config/rs6000/rs6000.cc
> +++ b/gcc/config/rs6000/rs6000.cc
> @@ -276,7 +276,7 @@ bool cpu_builtin_p = false;
> /* Pointer to function (in rs6000-c.cc) that can define or undefine target
> macros that have changed. Languages that don't support the preprocessor
> don't link in rs6000-c.cc, so we can't call it directly. */
> -void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT);
> +void (*rs6000_target_modify_macros_ptr) (bool, HOST_WIDE_INT, HOST_WIDE_INT);
>
> /* Simplfy register classes into simpler classifications. We assume
> GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
> @@ -1169,7 +1169,7 @@ enum reg_class (*rs6000_preferred_reload_class_ptr)
> (rtx, enum reg_class)
> const int INSN_NOT_AVAILABLE = -1;
>
> static void rs6000_print_isa_options (FILE *, int, const char *,
> - HOST_WIDE_INT);
> + HOST_WIDE_INT, HOST_WIDE_INT);
> static HOST_WIDE_INT rs6000_disable_incompatible_switches (void);
>
> static enum rs6000_reg_type register_to_reg_type (rtx, bool *);
> @@ -1792,13 +1792,18 @@ struct rs6000_ptt
> const char *const name; /* Canonical processor name. */
> const enum processor_type processor; /* Processor type enum value.
> */
> const HOST_WIDE_INT target_enable; /* Target flags to enable. */
> + const HOST_WIDE_INT cpu_isa; /* ISA flags set via
> -mcpu=<xxx>. */
> };
What would be the contents of cpu_isa? It will only contain the cpu level,
isn't it? IIUC, any other flags related to this cpu (say, a new feature
supported by the future cpu) will be kept in target_enable. So a better
naming will be cpu_level instead of cpu_isa. And also it should be treated
as an integer instead of as a mask.
My mental model of the changes we want to make to support -mcpu=future
while not having a -mfuture option is as follows:
1. Have a global flag (cpu_isa above) that sets the cpu level (based on
-mcpu= flag). The -mcpu= flag also sets some other flags which basically
represent the default option values for this cpu level (like pcrel, mma, or any
new features in the 'future' power processor etc.) These flags will be
represented in target_enable.
2. The compiler options are parsed to set the options flags (say the user
specifies -mno-pcrel, then the appropriate option flag in target_enable is
unset).
3. And then wherever we have to make decisions in gcc based on the cpu level,
just check the cpu_isa flag. And for features, check the options flags.
>
> static struct rs6000_ptt const processor_target_table[] =
> {
> -#define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
> +#undef RS6000_CPU_ISA
> +#define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS, 0 },
> +#define RS6000_CPU_ISA(NAME, CPU, FLAGS, CPU_ISA) \
> + { NAME, CPU, FLAGS, CPU_ISA },
> #include "rs6000-cpus.def"
> #undef RS6000_CPU
> +#undef RS6000_CPU_ISA
> };
>
Also, imho, we should have a different name than RS6000_CPU_NAME, because
this name doesn't convey what it actually means.
> /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
> @@ -2220,7 +2225,8 @@ rs6000_debug_print_mode (ssize_t m)
>
> #define DEBUG_FMT_ID "%-32s= "
> #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
> -#define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
> +#define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x" \
> + ", 0x%.2" HOST_WIDE_INT_PRINT "x: "
> #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
>
> /* Print various interesting information with -mdebug=reg. */
> @@ -2400,9 +2406,11 @@ rs6000_debug_reg_global (void)
> const char *name = processor_target_table[rs6000_cpu_index].name;
> HOST_WIDE_INT flags
> = processor_target_table[rs6000_cpu_index].target_enable;
> + HOST_WIDE_INT cpu_isa
> + = processor_target_table[rs6000_cpu_index].cpu_isa;
>
> sprintf (flags_buffer, "-mcpu=%s flags", name);
> - rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
> + rs6000_print_isa_options (stderr, 0, flags_buffer, flags, cpu_isa);
> }
> else
> fprintf (stderr, DEBUG_FMT_S, "cpu", "<none>");
> @@ -2414,19 +2422,19 @@ rs6000_debug_reg_global (void)
> = processor_target_table[rs6000_tune_index].target_enable;
>
> sprintf (flags_buffer, "-mtune=%s flags", name);
> - rs6000_print_isa_options (stderr, 0, flags_buffer, flags);
> + rs6000_print_isa_options (stderr, 0, flags_buffer, flags, 0);
> }
> else
> fprintf (stderr, DEBUG_FMT_S, "tune", "<none>");
>
> cl_target_option_save (&cl_opts, &global_options, &global_options_set);
> rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags",
> - rs6000_isa_flags);
> + rs6000_isa_flags, rs6000_cpu_isa_flags);
>
> rs6000_print_isa_options (stderr, 0, "rs6000_isa_flags_explicit",
> - rs6000_isa_flags_explicit);
> + rs6000_isa_flags_explicit, 0);
>
> - rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
> + rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT, 0);
>
> fprintf (stderr, DEBUG_FMT_S, "--with-cpu default",
> OPTION_TARGET_CPU_DEFAULT ? OPTION_TARGET_CPU_DEFAULT : "<none>");
> @@ -3623,7 +3631,7 @@ rs6000_option_override_internal (bool global_init_p)
>
> /* Print defaults. */
> if ((TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) && global_init_p)
> - rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT);
> + rs6000_print_isa_options (stderr, 0, "TARGET_DEFAULT", TARGET_DEFAULT,
> 0);
>
> /* Remember the explicit arguments. */
> if (global_init_p)
> @@ -3727,6 +3735,7 @@ rs6000_option_override_internal (bool global_init_p)
> rs6000_isa_flags &= ~set_masks;
> rs6000_isa_flags |= (processor_target_table[cpu_index].target_enable
> & set_masks);
> + rs6000_cpu_isa_flags = processor_target_table[cpu_index].cpu_isa;
> }
> else
> {
> @@ -3752,6 +3761,7 @@ rs6000_option_override_internal (bool global_init_p)
> flags = processor_target_table[default_cpu_index].target_enable;
> }
> rs6000_isa_flags |= (flags & ~rs6000_isa_flags_explicit);
> + rs6000_cpu_isa_flags = 0;
It would be good to set rs6000_cpu_isa_flags to the default cpu level
instead of making it 0.
Also, we should rename rs6000_cpu_isa_flags to rs6000_cpu_level.
> }
>
> /* Don't expect powerpc64 enabled on those OSes with OS_MISSING_POWERPC64,
> @@ -3873,7 +3883,8 @@ rs6000_option_override_internal (bool global_init_p)
> & ~rs6000_isa_flags_explicit);
>
> if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
> - rs6000_print_isa_options (stderr, 0, "before defaults",
> rs6000_isa_flags);
> + rs6000_print_isa_options (stderr, 0, "before defaults", rs6000_isa_flags,
We are printing more than just the isa options. So good to rename
rs6000_print_isa_options().
> + rs6000_cpu_isa_flags);
>
> #ifdef XCOFF_DEBUGGING_INFO
> /* For AIX default to 64-bit DWARF. */
> @@ -4234,7 +4245,8 @@ rs6000_option_override_internal (bool global_init_p)
>
> /* Print the options after updating the defaults. */
> if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
> - rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
> + rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags,
> + rs6000_cpu_isa_flags);
>
> /* E500mc does "better" if we inline more aggressively. Respect the
> user's opinion, though. */
> @@ -4341,7 +4353,8 @@ rs6000_option_override_internal (bool global_init_p)
> TARGET_NO_FP_IN_TOC = 1;
>
> if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
> - rs6000_print_isa_options (stderr, 0, "before subtarget",
> rs6000_isa_flags);
> + rs6000_print_isa_options (stderr, 0, "before subtarget",
> rs6000_isa_flags,
> + rs6000_cpu_isa_flags);
>
> #ifdef SUBTARGET_OVERRIDE_OPTIONS
> SUBTARGET_OVERRIDE_OPTIONS;
> @@ -4408,7 +4421,8 @@ rs6000_option_override_internal (bool global_init_p)
> rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT;
>
> if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
> - rs6000_print_isa_options (stderr, 0, "after subtarget",
> rs6000_isa_flags);
> + rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags,
> + rs6000_cpu_isa_flags);
>
> rs6000_always_hint = (rs6000_tune != PROCESSOR_POWER4
> && rs6000_tune != PROCESSOR_POWER5
> @@ -24508,6 +24522,11 @@ static struct rs6000_opt_mask const
> rs6000_opt_masks[] =
> { "string", 0, false,
> false },
> };
>
> +static struct rs6000_opt_mask const rs6000_cpu_isa_masks[] =
> +{
> + { "future", CPU_ISA_MASK_FUTURE, false,
> true },
> +};
> +
> /* Option variables that we want to support inside attribute((target)) and
> #pragma GCC target operations. */
>
> @@ -24866,6 +24885,7 @@ rs6000_pragma_target_parse (tree args, tree
> pop_target)
> tree cur_tree;
> struct cl_target_option *prev_opt, *cur_opt;
> HOST_WIDE_INT prev_flags, cur_flags, diff_flags;
> + HOST_WIDE_INT prev_cpu_isa, cur_cpu_isa, diff_cpu_isa;
>
> if (TARGET_DEBUG_TARGET)
> {
> @@ -24916,23 +24936,28 @@ rs6000_pragma_target_parse (tree args, tree
> pop_target)
> change the macros that are defined. */
> if (rs6000_target_modify_macros_ptr)
> {
> - prev_opt = TREE_TARGET_OPTION (prev_tree);
> - prev_flags = prev_opt->x_rs6000_isa_flags;
> + prev_opt = TREE_TARGET_OPTION (prev_tree);
> + prev_flags = prev_opt->x_rs6000_isa_flags;
> + prev_cpu_isa = prev_opt->x_rs6000_cpu_isa_flags;
>
> - cur_opt = TREE_TARGET_OPTION (cur_tree);
> - cur_flags = cur_opt->x_rs6000_isa_flags;
> + cur_opt = TREE_TARGET_OPTION (cur_tree);
> + cur_flags = cur_opt->x_rs6000_isa_flags;
> + cur_cpu_isa = cur_opt->x_rs6000_cpu_isa_flags;
>
> - diff_flags = (prev_flags ^ cur_flags);
> + diff_flags = (prev_flags ^ cur_flags);
> + diff_cpu_isa = (prev_cpu_isa ^ cur_cpu_isa);
>
> - if (diff_flags != 0)
> + if (diff_flags != 0 || diff_cpu_isa != 0)
> {
> /* Delete old macros. */
> rs6000_target_modify_macros_ptr (false,
> - prev_flags & diff_flags);
> + prev_flags & diff_flags,
> + prev_cpu_isa & diff_cpu_isa);
>
> /* Define new macros. */
> rs6000_target_modify_macros_ptr (true,
> - cur_flags & diff_flags);
> + cur_flags & diff_flags,
> + cur_cpu_isa & diff_cpu_isa);
> }
> }
>
> @@ -25068,10 +25093,11 @@ rs6000_function_specific_print (FILE *file, int
> indent,
> struct cl_target_option *ptr)
> {
> rs6000_print_isa_options (file, indent, "Isa options set",
> - ptr->x_rs6000_isa_flags);
> + ptr->x_rs6000_isa_flags,
> + ptr->x_rs6000_cpu_isa_flags);
>
> rs6000_print_isa_options (file, indent, "Isa options explicit",
> - ptr->x_rs6000_isa_flags_explicit);
> + ptr->x_rs6000_isa_flags_explicit, 0);
> }
>
> /* Helper function to print the current isa or misc options on a line. */
> @@ -25083,7 +25109,11 @@ rs6000_print_options_internal (FILE *file,
> HOST_WIDE_INT flags,
> const char *prefix,
> const struct rs6000_opt_mask *opts,
> - size_t num_elements)
> + size_t num_elements,
> + HOST_WIDE_INT cpu_isa,
> + const char *cpu_isa_prefix,
> + const struct rs6000_opt_mask *cpu_isa_opts,
> + size_t num_cpu_isa_elements)
> {
> size_t i;
> size_t start_column = 0;
> @@ -25096,13 +25126,13 @@ rs6000_print_options_internal (FILE *file,
> if (indent)
> start_column += fprintf (file, "%*s", indent, "");
>
> - if (!flags)
> + if (!flags && !cpu_isa)
> {
> fprintf (stderr, DEBUG_FMT_S, string, "<none>");
> return;
> }
>
> - start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags);
> + start_column += fprintf (stderr, DEBUG_FMT_WX, string, flags, cpu_isa);
>
> /* Print the various mask options. */
> cur_column = start_column;
> @@ -25149,6 +25179,33 @@ rs6000_print_options_internal (FILE *file,
> comma_len = strlen (", ");
> }
>
> + /* print the cpu isa bits that are set directly from -mcpu=<xxx> and there
> + is not an explicit -m<foo> option. We don't have to worry about
> inverting
> + options for the CPU ISA bits. */
> + for (i = 0; i < num_cpu_isa_elements; i++)
> + {
> + const char *name = cpu_isa_opts[i].name;
> + HOST_WIDE_INT mask = cpu_isa_opts[i].mask;
> + size_t len = comma_len + prefix_len + strlen (name);
> +
> + if ((cpu_isa & mask) != 0)
> + {
> + cpu_isa &= ~mask;
> +
> + cur_column += len;
> + if (cur_column > max_column)
> + {
> + fprintf (stderr, ", \\\n%*s", (int)start_column, "");
> + cur_column = start_column + len;
> + comma = "";
> + }
> +
> + fprintf (file, "%s%s%s", comma, cpu_isa_prefix, name);
> + comma = ", ";
> + comma_len = strlen (", ");
> + }
> + }
> +
> fputs ("\n", file);
> }
>
> @@ -25156,11 +25213,14 @@ rs6000_print_options_internal (FILE *file,
>
> static void
> rs6000_print_isa_options (FILE *file, int indent, const char *string,
> - HOST_WIDE_INT flags)
> + HOST_WIDE_INT flags, HOST_WIDE_INT cpu_isa)
> {
> rs6000_print_options_internal (file, indent, string, flags, "-m",
> &rs6000_opt_masks[0],
> - ARRAY_SIZE (rs6000_opt_masks));
> + ARRAY_SIZE (rs6000_opt_masks),
> + cpu_isa, "cpu-isa=",
> + &rs6000_cpu_isa_masks[0],
> + ARRAY_SIZE (rs6000_cpu_isa_masks));
> }
>
> /* If the user used -mno-vsx, we need turn off all of the implicit ISA 2.06,
> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
> index db6112a09e1..cffe2750ba9 100644
> --- a/gcc/config/rs6000/rs6000.h
> +++ b/gcc/config/rs6000/rs6000.h
> @@ -101,6 +101,7 @@
> you make changes here, make them also there. */
> #define ASM_CPU_SPEC \
> "%{mcpu=native: %(asm_cpu_native); \
> + mcpu=future: -mfuture; \
> mcpu=power11: -mpower11; \
> mcpu=power10: -mpower10; \
> mcpu=power9: -mpower9; \
> @@ -555,6 +556,12 @@ extern int rs6000_vector_align[];
> #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
> && TARGET_POWERPC64)
>
> +/* ISA bits that are set via -mcpu=<xxx>, but that do not have an associated
> + switch with the option. */
> +#define CPU_ISA_MASK_FUTURE 0x1 /* -mcpu=future used. */
If we hardcode value of 1 here for 'future', then what values will we use for
P10,
P9 etc?
Perhaps better to use the enum values in 'enum processor_type'? (of course, we
would then need to add an entry for PROCESSOR_FUTURE).
Regards,
Surya
> +
> +#define TARGET_FUTURE (rs6000_cpu_isa_flags &
> CPU_ISA_MASK_FUTURE)
> +
> /* Inlining allows targets to define the meanings of bits in target_info
> field of ipa_fn_summary by itself, the used bits for rs6000 are listed
> below. */
> diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
> index 88cf16ca581..39ae7791c60 100644
> --- a/gcc/config/rs6000/rs6000.opt
> +++ b/gcc/config/rs6000/rs6000.opt
> @@ -36,6 +36,14 @@ HOST_WIDE_INT rs6000_isa_flags_explicit
> TargetSave
> HOST_WIDE_INT x_rs6000_isa_flags_explicit
>
> +;; CPU ISA flag bits (on/off) that are enabled with the -mcpu= option,
> +;; but do not have an explicit option attached to the ISA bit.
> +Variable
> +HOST_WIDE_INT rs6000_cpu_isa_flags = 0
> +
> +TargetSave
> +HOST_WIDE_INT x_rs6000_cpu_isa_flags
> +
> ;; Current processor
> TargetVariable
> enum processor_type rs6000_cpu = PROCESSOR_PPC603
