Re: [PATCH] RISC-V: Adjust tt-ascalon-d8 branch cost

[Jeff Law]

On 9/7/25 3:19 PM, Anton Blanchard wrote:

If-conversion isn't being applied to this nbench code:

  #include <stdint.h>
  #define INTERNAL_FPF_PRECISION 4
  typedef uint16_t u16;

  void ShiftMantLeft1(u16 *carry, u16 *mantissa)
  {
          int i;
          int new_carry;
          u16 accum;

          for(i=INTERNAL_FPF_PRECISION-1;i>=0;i--)
          {       accum=mantissa[i];
                  new_carry=accum & 0x8000;
                  accum=accum<<1;
                  if(*carry)
                          accum|=1;
                  *carry=new_carry;
                  mantissa[i]=accum;
          }
          return;
  }

Bumping branch_cost from 3 to 4 triggers if-conversion, improving the
nbench FP EMULATION result on Ascalon significantly. There's a risk
that more aggressive use of conditional zero instructions will negatively
impact workloads that predict well, but we haven't seen anything obvious.

gcc/ChangeLog:
        * config/riscv/riscv.cc (tt_ascalon_d8_tune_info): Increase branch_cost
        from 3 to 4.

I've pushed this to the trunk.
JEff