On Sat, 6 Sep 2025, Jeff Law wrote: > > The patch now includes: > > > > - Skipping of affected tests for MIPS16/microMIPS. > > - Addition of `check_effective_target_mips_compressed` in > > `target-supports.exp`. > > - Documentation of `mips_compressed` in `sourcebuild.texi`. > IIRC mips16 isn't really meant to be used standalone, so in the real world > this > really isn't a problem, it's really an artifact of trying to run the entire > testsuite in mips16 mode? Or am I missing something. Just want to make sure I > understand the motivation here.
True, however microMIPS code can run standalone; a pure microMIPS CPU core is also feasible by the spec, including the privileged ISA (important for exception vectors, which need to handle compressed code), although I'm not sure whether one has ever been taped out. Such an implementation will trap on control transfer instructions trying to switch to the regular MIPS ISA mode (JR, JALX, etc.). That alone ought to justify the need to get things sorted here, although actually both `-mmicromips' and `-mips16' multilibs exist in the field (I can't remember offhand how things are arranged in the latter case for bits that need to run in the regular MIPS ISA mode; it boils down to preventing the tail call optimisation from triggering for control transfers between ISA modes as there's no JX direct jump plus mode switch instruction in the ISA (indirect jumps are OK as they update the ISA bit explicitly), which is the very issue triggered by these test cases). Please also have a look at my observation elsewhere in this thread as to how I think this regression ought to be properly sorted. Maciej
