Hi Kito,
On 02/09/2025 12:01, Paul-Antoine Arras wrote:
Hi Kito,
On 02/09/2025 05:17, Kito Cheng wrote:
Hi Paul-Antoine:
diff --git gcc/config/riscv/autovec-opt.md gcc/config/riscv/autovec-
opt.md
index d56fb5f237c..5cb34cef418 100644
--- gcc/config/riscv/autovec-opt.md
+++ gcc/config/riscv/autovec-opt.md
@@ -2163,3 +2163,41 @@ (define_insn_and_split "*vfmax_vf_<mode>"
}
[(set_attr "type" "vfminmax")]
)
+
+(define_insn_and_split "*vfmax_vf_ieee_<mode>"
+ [(set (match_operand:V_VLSF 0 "register_operand")
+ (unspec:V_VLSF [
+ (vec_duplicate:V_VLSF
+ (match_operand:<VEL> 2 "register_operand"))
+ (match_operand:V_VLSF 1 "register_operand")
+ ] UNSPEC_VFMAX))]
+ "TARGET_VECTOR && !HONOR_SNANS (<MODE>mode) && can_create_pseudo_p
()"
Could you try to use the iterator to merge the pattern with vfmin_vf?
you can grep UNSPEC_VFMAXMIN and see the example in vector.md
Is it OK with the change mentioned below?
I have attached an amended patch as you suggested. Here is the relevant
snippet:
(define_insn_and_split "*v<ieee_fmaxmin_op>_vf_<mode>"
[(set (match_operand:V_VLSF 0 "register_operand")
(unspec:V_VLSF [
(vec_duplicate:V_VLSF
(match_operand:<VEL> 2 "register_operand"))
(match_operand:V_VLSF 1 "register_operand")
] UNSPEC_VFMAXMIN))]
"TARGET_VECTOR && !HONOR_SNANS (<MODE>mode) && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
{
riscv_vector::emit_vlmax_insn (code_for_pred_scalar
(<IEEE_FMAXMIN_OP>,
<MODE>mode),
riscv_vector::BINARY_OP, operands);
DONE;
}
[(set_attr "type" "vfminmax")]
)
(define_insn_and_split "*v<ieee_fmaxmin_op>_vf_<mode>"
[(set (match_operand:V_VLSF 0 "register_operand")
(unspec:V_VLSF [
(match_operand:V_VLSF 1 "register_operand")
(vec_duplicate:V_VLSF
(match_operand:<VEL> 2 "register_operand"))
] UNSPEC_VFMAXMIN))]
"TARGET_VECTOR && !HONOR_SNANS (<MODE>mode) && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
{
riscv_vector::emit_vlmax_insn (code_for_pred_scalar
(<IEEE_FMAXMIN_OP>,
<MODE>mode),
riscv_vector::BINARY_OP, operands);
DONE;
}
[(set_attr "type" "vfminmax")]
)
--
PA
