On 02/09/2025 16:16, Jeff Law wrote:
On 9/1/25 5:07 AM, Paul-Antoine Arras wrote:
This pattern enables the combine pass (or late-combine, depending on
the case)
to merge a vec_duplicate into an smax RTL instruction.
[ ... ]
diff --git gcc/config/riscv/autovec-opt.md gcc/config/riscv/autovec-
opt.md
index 9695fdcb5c9..d56fb5f237c 100644
--- gcc/config/riscv/autovec-opt.md
+++ gcc/config/riscv/autovec-opt.md
@@ -2144,3 +2144,22 @@ (define_insn_and_split "*vfmin_vf_ieee_<mode>"
}
[(set_attr "type" "vfminmax")]
)
+
+;; vfmax.vf
+(define_insn_and_split "*vfmax_vf_<mode>"
+ [(set (match_operand:V_VLSF 0 "register_operand")
+ (smax:V_VLSF
+ (vec_duplicate:V_VLSF
+ (match_operand:<VEL> 2 "register_operand"))
+ (match_operand:V_VLSF 1 "register_operand")))]
+ "TARGET_VECTOR && can_create_pseudo_p ()"
+ "#"
+ "&& 1"
+ [(const_int 0)]
+ {
+ riscv_vector::emit_vlmax_insn (code_for_pred_scalar (SMAX,
<MODE>mode),
+ riscv_vector::BINARY_OP, operands);
+ DONE;
+ }
+ [(set_attr "type" "vfminmax")]
So much like the IEEE variant that Kito commented on, this may be best
folded into the recently added vfmin_vf_<mode> pattern. You'd want to
use an iterator on the code that expands to smin/smax and a
corresponding change to to the emit_vlmax_insn call.
Here is the updated patch. The relevant snippet is now:
(define_insn_and_split "*vf<optab>_vf_<mode>"
[(set (match_operand:V_VLSF 0 "register_operand")
(commutative_float_binop_nofrm:V_VLSF
(vec_duplicate:V_VLSF
(match_operand:<VEL> 2 "register_operand"))
(match_operand:V_VLSF 1 "register_operand")))]
"TARGET_VECTOR && can_create_pseudo_p ()"
"#"
"&& 1"
[(const_int 0)]
{
riscv_vector::emit_vlmax_insn (code_for_pred_scalar (<CODE>,
<MODE>mode),
riscv_vector::BINARY_OP, operands);
DONE;
}
[(set_attr "type" "vfminmax")]
)
--
PAcommit 0552d9ff9b826b332a1b5dd08e6d1c9a68ede155
Author: Paul-Antoine Arras <[email protected]>
Date: Mon Sep 1 11:39:41 2025 +0200
RISC-V: Add pattern for vector-scalar floating-point max
This pattern enables the combine pass (or late-combine, depending on the case)
to merge a vec_duplicate into an smax RTL instruction.
Before this patch, we have two instructions, e.g.:
vfmv.v.f v2,fa0
vfmax.vv v1,v1,v2
After, we get only one:
vfmax.vf v1,v1,fa0
In some cases, it also shaves off one vsetvli.
gcc/ChangeLog:
* config/riscv/autovec-opt.md (*vfmax_vf_<mode>): Rename into...
(*vf<optab>_vf_<mode>): New pattern to combine vec_duplicate +
vf{min,max}.vv into vf{max,min}.vf.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c: Adjust scan
dump.
* gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfmax. Also add
missing scan-dump for vfmul.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Add vfmax.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h: Add max functions.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h: Add data for
vfmax.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmax-run-1-f16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmax-run-1-f32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmax-run-1-f64.c: New test.
diff --git gcc/config/riscv/autovec-opt.md gcc/config/riscv/autovec-opt.md
index 9695fdcb5c9..80b3b78d53b 100644
--- gcc/config/riscv/autovec-opt.md
+++ gcc/config/riscv/autovec-opt.md
@@ -2088,10 +2088,10 @@ (define_insn_and_split "*vfrdiv_vf_<mode>"
[(set_attr "type" "vfdiv")]
)
-;; vfmin.vf
-(define_insn_and_split "*vfmin_vf_<mode>"
+;; vfmin.vf, vfmax.vf
+(define_insn_and_split "*vf<optab>_vf_<mode>"
[(set (match_operand:V_VLSF 0 "register_operand")
- (smin:V_VLSF
+ (commutative_float_binop_nofrm:V_VLSF
(vec_duplicate:V_VLSF
(match_operand:<VEL> 2 "register_operand"))
(match_operand:V_VLSF 1 "register_operand")))]
@@ -2100,7 +2100,7 @@ (define_insn_and_split "*vfmin_vf_<mode>"
"&& 1"
[(const_int 0)]
{
- riscv_vector::emit_vlmax_insn (code_for_pred_scalar (SMIN, <MODE>mode),
+ riscv_vector::emit_vlmax_insn (code_for_pred_scalar (<CODE>, <MODE>mode),
riscv_vector::BINARY_OP, operands);
DONE;
}
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c
index 8dc5a31de24..fd118357a1b 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-2.c
@@ -39,5 +39,5 @@ DEF_MINMAX_VX (max, 128, double, >)
DEF_MINMAX_VX (max, 256, double, >)
DEF_MINMAX_VX (max, 512, double, >)
-/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c
index db3bf8667bb..eb0edac5fe0 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-max-4.c
@@ -39,5 +39,5 @@ DEF_MINMAX_VX (max, 128, double, >=)
DEF_MINMAX_VX (max, 256, double, >=)
DEF_MINMAX_VX (max, 512, double, >=)
-/* { dg-final { scan-assembler-times {vfmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
+/* { dg-final { scan-assembler-times {vfmax\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */
/* { dg-final { scan-assembler-not {csrr} } } */
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
index 7e56330d9f2..0be64f1fd64 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
@@ -20,6 +20,8 @@ DEF_VF_BINOP_CASE_0 (_Float16, *, mul)
DEF_VF_BINOP_REVERSE_CASE_0 (_Float16, /, rdiv)
DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_0_WRAP (_Float16), min)
DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_1_WRAP (_Float16), min)
+DEF_VF_BINOP_CASE_2_WRAP (_Float16, MAX_FUNC_0_WRAP (_Float16), max)
+DEF_VF_BINOP_CASE_2_WRAP (_Float16, MAX_FUNC_1_WRAP (_Float16), max)
/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
@@ -33,5 +35,7 @@ DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_1_WRAP (_Float16), min)
/* { dg-final { scan-assembler-times {vfwmsac.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */
+/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
+/* { dg-final { scan-assembler-times {vfmax.vf} 2 } } */
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
index e674cf7245a..a9cd38aebeb 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
@@ -20,6 +20,8 @@ DEF_VF_BINOP_CASE_0 (float, *, mul)
DEF_VF_BINOP_REVERSE_CASE_0 (float, /, rdiv)
DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_0_WRAP (float), min)
DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_1_WRAP (float), min)
+DEF_VF_BINOP_CASE_2_WRAP (float, MAX_FUNC_0_WRAP (float), max)
+DEF_VF_BINOP_CASE_2_WRAP (float, MAX_FUNC_1_WRAP (float), max)
/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
@@ -36,3 +38,4 @@ DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_1_WRAP (float), min)
/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
+/* { dg-final { scan-assembler-times {vfmax.vf} 2 } } */
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
index b36e966c21c..4eb4a4e4b06 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
@@ -16,6 +16,8 @@ DEF_VF_BINOP_CASE_0 (double, *, mul)
DEF_VF_BINOP_REVERSE_CASE_0 (double, /, rdiv)
DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_0_WRAP (double), min)
DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_1_WRAP (double), min)
+DEF_VF_BINOP_CASE_2_WRAP (double, MAX_FUNC_0_WRAP (double), max)
+DEF_VF_BINOP_CASE_2_WRAP (double, MAX_FUNC_1_WRAP (double), max)
/* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
@@ -28,3 +30,4 @@ DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_1_WRAP (double), min)
/* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
+/* { dg-final { scan-assembler-times {vfmax.vf} 2 } } */
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
index 1914b18643c..0db3048688c 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
@@ -18,4 +18,5 @@
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */
/* { dg-final { scan-assembler-times {fcvt.s.h} 4 } } */
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
index f8dab374962..494b33e45b2 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
@@ -18,4 +18,5 @@
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */
/* { dg-final { scan-assembler-times {fcvt.d.s} 4 } } */
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
index 909770f7071..ffffde7a8a3 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
@@ -14,3 +14,4 @@
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
index c703ed67860..c2c4f430b15 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
@@ -22,6 +22,10 @@ DEF_VF_BINOP_CASE_3_WRAP (_Float16, MIN_FUNC_0_WRAP (_Float16), min,
VF_BINOP_FUNC_BODY_X128)
DEF_VF_BINOP_CASE_3_WRAP (_Float16, MIN_FUNC_1_WRAP (_Float16), min,
VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (_Float16, MAX_FUNC_0_WRAP (_Float16), max,
+ VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (_Float16, MAX_FUNC_1_WRAP (_Float16), max,
+ VF_BINOP_FUNC_BODY_X128)
/* { dg-final { scan-assembler {vfmadd.vf} } } */
/* { dg-final { scan-assembler {vfmsub.vf} } } */
@@ -38,3 +42,4 @@ DEF_VF_BINOP_CASE_3_WRAP (_Float16, MIN_FUNC_1_WRAP (_Float16), min,
/* { dg-final { scan-assembler {vfmul.vf} } } */
/* { dg-final { scan-assembler {vfrdiv.vf} } } */
/* { dg-final { scan-assembler {vfmin.vf} } } */
+/* { dg-final { scan-assembler {vfmax.vf} } } */
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
index 99b84dd681b..f2582cad8b3 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
@@ -22,6 +22,10 @@ DEF_VF_BINOP_CASE_3_WRAP (float, MIN_FUNC_0_WRAP (float), min,
VF_BINOP_FUNC_BODY_X128)
DEF_VF_BINOP_CASE_3_WRAP (float, MIN_FUNC_1_WRAP (float), min,
VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (float, MAX_FUNC_0_WRAP (float), max,
+ VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (float, MAX_FUNC_1_WRAP (float), max,
+ VF_BINOP_FUNC_BODY_X128)
/* { dg-final { scan-assembler {vfmadd.vf} } } */
/* { dg-final { scan-assembler {vfmsub.vf} } } */
@@ -38,3 +42,4 @@ DEF_VF_BINOP_CASE_3_WRAP (float, MIN_FUNC_1_WRAP (float), min,
/* { dg-final { scan-assembler {vfmul.vf} } } */
/* { dg-final { scan-assembler {vfrdiv.vf} } } */
/* { dg-final { scan-assembler {vfmin.vf} } } */
+/* { dg-final { scan-assembler {vfmax.vf} } } */
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
index 889fed2c83a..831646f6a40 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
@@ -18,6 +18,10 @@ DEF_VF_BINOP_CASE_3_WRAP (double, MIN_FUNC_0_WRAP (double), min,
VF_BINOP_FUNC_BODY_X128)
DEF_VF_BINOP_CASE_3_WRAP (double, MIN_FUNC_1_WRAP (double), min,
VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (double, MAX_FUNC_0_WRAP (double), max,
+ VF_BINOP_FUNC_BODY_X128)
+DEF_VF_BINOP_CASE_3_WRAP (double, MAX_FUNC_1_WRAP (double), max,
+ VF_BINOP_FUNC_BODY_X128)
/* { dg-final { scan-assembler {vfmadd.vf} } } */
/* { dg-final { scan-assembler {vfmsub.vf} } } */
@@ -30,3 +34,4 @@ DEF_VF_BINOP_CASE_3_WRAP (double, MIN_FUNC_1_WRAP (double), min,
/* { dg-final { scan-assembler {vfmul.vf} } } */
/* { dg-final { scan-assembler {vfrdiv.vf} } } */
/* { dg-final { scan-assembler {vfmin.vf} } } */
+/* { dg-final { scan-assembler {vfmax.vf} } } */
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
index 9db8736daed..3fa31504cfe 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f16.c
@@ -18,4 +18,5 @@
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */
/* { dg-final { scan-assembler {fcvt.s.h} } } */
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
index 577ad8da232..3d526b56e01 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f32.c
@@ -18,4 +18,5 @@
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */
/* { dg-final { scan-assembler {fcvt.d.s} } } */
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
index 30e5660fe81..d29006e5849 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-4-f64.c
@@ -14,3 +14,4 @@
/* { dg-final { scan-assembler-not {vfmul.vf} } } */
/* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
/* { dg-final { scan-assembler-not {vfmin.vf} } } */
+/* { dg-final { scan-assembler-not {vfmax.vf} } } */
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
index 90436a298c2..da02065dda8 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
@@ -130,6 +130,12 @@
#define DEF_MIN_1(T) \
static inline T test_##T##_min_1 (T a, T b) { return a >= b ? b : a; }
+#define DEF_MAX_0(T) \
+ static inline T test_##T##_max_0 (T a, T b) { return a > b ? a : b; }
+
+#define DEF_MAX_1(T) \
+ static inline T test_##T##_max_1 (T a, T b) { return a >= b ? a : b; }
+
DEF_MIN_0 (_Float16)
DEF_MIN_0 (float)
DEF_MIN_0 (double)
@@ -138,12 +144,26 @@ DEF_MIN_1 (_Float16)
DEF_MIN_1 (float)
DEF_MIN_1 (double)
+DEF_MAX_0 (_Float16)
+DEF_MAX_0 (float)
+DEF_MAX_0 (double)
+
+DEF_MAX_1 (_Float16)
+DEF_MAX_1 (float)
+DEF_MAX_1 (double)
+
#define MIN_FUNC_0(T) test_##T##_min_0
#define MIN_FUNC_0_WRAP(T) MIN_FUNC_0 (T)
#define MIN_FUNC_1(T) test_##T##_min_1
#define MIN_FUNC_1_WRAP(T) MIN_FUNC_1 (T)
+#define MAX_FUNC_0(T) test_##T##_max_0
+#define MAX_FUNC_0_WRAP(T) MAX_FUNC_0 (T)
+
+#define MAX_FUNC_1(T) test_##T##_max_1
+#define MAX_FUNC_1_WRAP(T) MAX_FUNC_1 (T)
+
#define DEF_VF_BINOP_CASE_2(T, FUNC, NAME) \
void test_vf_binop_##NAME##_##FUNC##_##T##_case_2 (T *restrict out, \
T *restrict in, T f, \
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
index e6ddd1ebb4f..2f79cee16ca 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
@@ -447,5 +447,151 @@ double TEST_BINOP_DATA(double, min)[][4][N] =
},
},
};
+_Float16 TEST_BINOP_DATA(_Float16, max)[][4][N] =
+{
+ {
+ { 0x1.e000000000000p+4f16 },
+ {
+ 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16,
+ 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16,
+ 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16,
+ 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16,
+ },
+ {
+ 0x1.e000000000000p+4f16, 0x1.e000000000000p+4f16, 0x1.e000000000000p+4f16, 0x1.e000000000000p+4f16,
+ 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16,
+ 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16,
+ 0x1.e000000000000p+4f16, 0x1.e000000000000p+4f16, 0x1.e000000000000p+4f16, 0x1.e000000000000p+4f16,
+ },
+ },
+ {
+ { -0x1.e000000000000p+4f16 },
+ {
+ -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
+ 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16,
+ -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
+ -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
+ },
+ {
+ -0x1.e000000000000p+4f16, -0x1.e000000000000p+4f16, -0x1.e000000000000p+4f16, -0x1.e000000000000p+4f16,
+ 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16,
+ -0x1.e000000000000p+4f16, -0x1.e000000000000p+4f16, -0x1.e000000000000p+4f16, -0x1.e000000000000p+4f16,
+ -0x1.e000000000000p+4f16, -0x1.e000000000000p+4f16, -0x1.e000000000000p+4f16, -0x1.e000000000000p+4f16,
+ },
+ },
+ {
+ { -0x0.0p+0f16 },
+ {
+ -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
+ 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16,
+ -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
+ -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
+ },
+ {
+ -0x0.0p+0f16, -0x0.0p+0f16, -0x0.0p+0f16, -0x0.0p+0f16,
+ 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16,
+ -0x0.0p+0f16, -0x0.0p+0f16, -0x0.0p+0f16, -0x0.0p+0f16,
+ -0x0.0p+0f16, -0x0.0p+0f16, -0x0.0p+0f16, -0x0.0p+0f16,
+ },
+ },
+};
+
+float TEST_BINOP_DATA(float, max)[][4][N] =
+{
+ {
+ { 0x1.4d11200000000p+61f },
+ {
+ 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f,
+ 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f,
+ 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f,
+ 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f,
+ },
+ {
+ 0x1.4d11200000000p+61f, 0x1.4d11200000000p+61f, 0x1.4d11200000000p+61f, 0x1.4d11200000000p+61f,
+ 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f,
+ 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f,
+ 0x1.4d11200000000p+61f, 0x1.4d11200000000p+61f, 0x1.4d11200000000p+61f, 0x1.4d11200000000p+61f,
+ },
+ },
+ {
+ { 0x1.0000000000000p+0f },
+ {
+ -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f,
+ 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f,
+ -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f,
+ -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f,
+ },
+ {
+ 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f,
+ 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f,
+ 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f,
+ 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f,
+ },
+ },
+ {
+ { -0x0.0p+0f },
+ {
+ -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f, -0x1.062a340000000p+61f,
+ -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f, -0x1.e573960000000p+63f,
+ 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f,
+ -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f,
+ },
+ {
+ -0x0.0p+0f, -0x0.0p+0f, -0x0.0p+0f, -0x0.0p+0f,
+ -0x0.0p+0f, -0x0.0p+0f, -0x0.0p+0f, -0x0.0p+0f,
+ 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f,
+ -0x0.0p+0f, -0x0.0p+0f, -0x0.0p+0f, -0x0.0p+0f,
+ },
+ },
+};
+
+double TEST_BINOP_DATA(double, max)[][4][N] =
+{
+ {
+ { 0x1.317e5ef3ab327p+509 },
+ {
+ 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508,
+ 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510,
+ 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509,
+ 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508,
+ },
+ {
+ 0x1.317e5ef3ab327p+509, 0x1.317e5ef3ab327p+509, 0x1.317e5ef3ab327p+509, 0x1.317e5ef3ab327p+509,
+ 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510,
+ 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509,
+ 0x1.317e5ef3ab327p+509, 0x1.317e5ef3ab327p+509, 0x1.317e5ef3ab327p+509, 0x1.317e5ef3ab327p+509,
+ },
+ },
+ {
+ { 0x1.0000000000000p+0 },
+ {
+ -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509,
+ 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510,
+ -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511,
+ -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510,
+ },
+ {
+ 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0,
+ 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510,
+ 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0,
+ 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0,
+ },
+ },
+ {
+ { -0x1.317e5ef3ab327p+509 },
+ {
+ -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509,
+ -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511,
+ 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508,
+ -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509,
+ },
+ {
+ -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509,
+ -0x1.317e5ef3ab327p+509, -0x1.317e5ef3ab327p+509, -0x1.317e5ef3ab327p+509, -0x1.317e5ef3ab327p+509,
+ 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508,
+ -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509,
+ },
+ },
+};
#endif
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmax-run-1-f16.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmax-run-1-f16.c
new file mode 100644
index 00000000000..99655233ee5
--- /dev/null
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmax-run-1-f16.c
@@ -0,0 +1,20 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-require-effective-target riscv_v_ok } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
+/* { dg-add-options "riscv_v" } */
+/* { dg-add-options "riscv_zvfh" } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T _Float16
+#define FUNC MAX_FUNC_0_WRAP(T)
+#define NAME max
+
+DEF_VF_BINOP_CASE_2_WRAP (T, FUNC, NAME)
+
+#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_2_WRAP(T, NAME, FUNC, out, in, f, n)
+
+#include "vf_binop_run.h"
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmax-run-1-f32.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmax-run-1-f32.c
new file mode 100644
index 00000000000..5394f183821
--- /dev/null
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmax-run-1-f32.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T float
+#define FUNC MAX_FUNC_0_WRAP(T)
+#define NAME max
+
+DEF_VF_BINOP_CASE_2_WRAP (T, FUNC, NAME)
+
+#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_2_WRAP(T, NAME, FUNC, out, in, f, n)
+
+#include "vf_binop_run.h"
diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmax-run-1-f64.c gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmax-run-1-f64.c
new file mode 100644
index 00000000000..b3df50f1b05
--- /dev/null
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmax-run-1-f64.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "--param=fpr2vr-cost=0" } */
+
+#include "vf_binop.h"
+#include "vf_binop_data.h"
+
+#define T double
+#define FUNC MAX_FUNC_0_WRAP(T)
+#define NAME max
+
+DEF_VF_BINOP_CASE_2_WRAP (T, FUNC, NAME)
+
+#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_2_WRAP(T, NAME, FUNC, out, in, f, n)
+
+#include "vf_binop_run.h"
