Paul-Antoine Arras <[email protected]>於 2025年8月28日 週四，01:50寫道：
> This pattern enables the combine pass (or late-combine, depending on the
> case)
> to merge a vec_duplicate into an smin RTL instruction.
>
> Before this patch, we have two instructions, e.g.:
> vfmv.v.f v2,fa0
> vfmin.vv v1,v1,v2
>
> After, we get only one:
> vfmin.vf v1,v1,fa0
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md (*vfmin_vf_<mode>): Add new pattern
> to
> combine vec_duplicate + vfmin.vv into vfmin.vf.
> * config/riscv/vector.md (@pred_<optab><mode>_scalar): Allow VLS
> modes.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c: Adjust
> scan
> dump.
> * gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c:
> Likewise.
> * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c: Add vfmin.
> * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c: Likewise.
> * gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c: Likewise.
> * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c: Likewise.
> * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c: Likewise.
> * gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c: Likewise.
> * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c: Likewise.
> * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c: Likewise.
> * gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c: Likewise.
> * gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h: Add support for
> function variants.
> * gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h: Add data for
> vfmin.
> * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c: New
> test.
> * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c: New
> test.
> * gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c: New
> test.
> ---
> gcc/config/riscv/autovec-opt.md | 19 +++
> gcc/config/riscv/vector.md | 24 +--
> .../rvv/autovec/vls/floating-point-min-2.c | 2 +-
> .../rvv/autovec/vls/floating-point-min-4.c | 2 +-
> .../riscv/rvv/autovec/vx_vf/vf-1-f16.c | 3 +
> .../riscv/rvv/autovec/vx_vf/vf-1-f32.c | 3 +
> .../riscv/rvv/autovec/vx_vf/vf-1-f64.c | 3 +
> .../riscv/rvv/autovec/vx_vf/vf-2-f16.c | 2 +-
> .../riscv/rvv/autovec/vx_vf/vf-2-f32.c | 2 +-
> .../riscv/rvv/autovec/vx_vf/vf-2-f64.c | 1 +
> .../riscv/rvv/autovec/vx_vf/vf-3-f16.c | 5 +
> .../riscv/rvv/autovec/vx_vf/vf-3-f32.c | 5 +
> .../riscv/rvv/autovec/vx_vf/vf-3-f64.c | 5 +
> .../riscv/rvv/autovec/vx_vf/vf_binop.h | 81 ++++++++++
> .../riscv/rvv/autovec/vx_vf/vf_binop_data.h | 147 ++++++++++++++++++
> .../rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c | 20 +++
> .../rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c | 16 ++
> .../rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c | 16 ++
> 18 files changed, 340 insertions(+), 16 deletions(-)
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c
>
> diff --git gcc/config/riscv/autovec-opt.md gcc/config/riscv/autovec-opt.md
> index 29bdfc3d90f..1440eeaea90 100644
> --- gcc/config/riscv/autovec-opt.md
> +++ gcc/config/riscv/autovec-opt.md
> @@ -2065,3 +2065,22 @@ (define_insn_and_split "*vfrdiv_vf_<mode>"
> }
> [(set_attr "type" "vfmuladd")]
> )
> +
> +;; vfmin.vf
> +(define_insn_and_split "*vfmin_vf_<mode>"
> + [(set (match_operand:V_VLSF 0 "register_operand")
> + (smin:V_VLSF
> + (vec_duplicate:V_VLSF
> + (match_operand:<VEL> 2 "register_operand"))
> + (match_operand:V_VLSF 1 "register_operand")))]
> + "TARGET_VECTOR && can_create_pseudo_p ()"
> + "#"
> + "&& 1"
> + [(const_int 0)]
> + {
> + riscv_vector::emit_vlmax_insn (code_for_pred_scalar (SMIN,
> <MODE>mode),
> + riscv_vector::BINARY_OP, operands);
> + DONE;
> + }
> + [(set_attr "type" "vfmuladd")]
this seems incorrect, otherwise LGTM
>
> +)
> diff --git gcc/config/riscv/vector.md gcc/config/riscv/vector.md
> index e7ffeeb9cd6..913a775eec7 100644
> --- gcc/config/riscv/vector.md
> +++ gcc/config/riscv/vector.md
> @@ -6395,21 +6395,21 @@ (define_insn "@pred_<optab><mode>_scalar"
> (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
>
> (define_insn "@pred_<optab><mode>_scalar"
> - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr,
> vr")
> - (if_then_else:VF
> + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd,
> vr, vr")
> + (if_then_else:V_VLSF
> (unspec:<VM>
> - [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
> - (match_operand 5 "vector_length_operand" "rvl,rvl,rvl,rvl")
> - (match_operand 6 "const_int_operand" " i, i, i, i")
> - (match_operand 7 "const_int_operand" " i, i, i, i")
> - (match_operand 8 "const_int_operand" " i, i, i, i")
> + [(match_operand:<VM> 1 "vector_mask_operand" " vm,
> vm,Wc1,Wc1")
> + (match_operand 5 "vector_length_operand"
> "rvl,rvl,rvl,rvl")
> + (match_operand 6 "const_int_operand" " i, i,
> i, i")
> + (match_operand 7 "const_int_operand" " i, i,
> i, i")
> + (match_operand 8 "const_int_operand" " i, i,
> i, i")
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> - (commutative_float_binop_nofrm:VF
> - (vec_duplicate:VF
> - (match_operand:<VEL> 4 "register_operand" " f, f, f,
> f"))
> - (match_operand:VF 3 "register_operand" " vr, vr, vr,
> vr"))
> - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu,
> 0")))]
> + (commutative_float_binop_nofrm:V_VLSF
> + (vec_duplicate:V_VLSF
> + (match_operand:<VEL> 4 "register_operand" " f, f,
> f, f"))
> + (match_operand:V_VLSF 3 "register_operand" " vr, vr, vr,
> vr"))
> + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0,
> vu, 0")))]
> "TARGET_VECTOR"
> "vf<insn>.vf\t%0,%3,%4%p1"
> [(set_attr "type" "<float_insn_type>")
> diff --git
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
> index 101ad573aef..2953d18c647 100644
> --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
> +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-2.c
> @@ -39,5 +39,5 @@ DEF_MINMAX_VX (min, 128, double, <)
> DEF_MINMAX_VX (min, 256, double, <)
> DEF_MINMAX_VX (min, 512, double, <)
>
> -/* { dg-final { scan-assembler-times
> {vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
> +/* { dg-final { scan-assembler-times
> {vfmin\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */
> /* { dg-final { scan-assembler-not {csrr} } } */
> diff --git
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
> index 004a95cd05d..db156ac23b5 100644
> --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
> +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-min-4.c
> @@ -39,5 +39,5 @@ DEF_MINMAX_VX (min, 128, double, <=)
> DEF_MINMAX_VX (min, 256, double, <=)
> DEF_MINMAX_VX (min, 512, double, <=)
>
> -/* { dg-final { scan-assembler-times
> {vfmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */
> +/* { dg-final { scan-assembler-times
> {vfmin\.vf\s+v[0-9]+,\s*v[0-9]+,\s*f[ast]?[0-9]+} 30 } } */
> /* { dg-final { scan-assembler-not {csrr} } } */
> diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
> index bbbbc52a781..7e56330d9f2 100644
> --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
> +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f16.c
> @@ -18,6 +18,8 @@ DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, +, -, nacc)
> DEF_VF_MULOP_WIDEN_CASE_0 (_Float16, float, -, -, nsac)
> DEF_VF_BINOP_CASE_0 (_Float16, *, mul)
> DEF_VF_BINOP_REVERSE_CASE_0 (_Float16, /, rdiv)
> +DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_0_WRAP (_Float16), min)
> +DEF_VF_BINOP_CASE_2_WRAP (_Float16, MIN_FUNC_1_WRAP (_Float16), min)
>
> /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
> /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
> @@ -32,3 +34,4 @@ DEF_VF_BINOP_REVERSE_CASE_0 (_Float16, /, rdiv)
> /* { dg-final { scan-assembler-times {vfwnmacc.vf} 1 } } */
> /* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */
> /* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
> +/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
> diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
> index 912c037126d..e674cf7245a 100644
> --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
> +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f32.c
> @@ -18,6 +18,8 @@ DEF_VF_MULOP_WIDEN_CASE_0 (float, double, +, -, nacc)
> DEF_VF_MULOP_WIDEN_CASE_0 (float, double, -, -, nsac)
> DEF_VF_BINOP_CASE_0 (float, *, mul)
> DEF_VF_BINOP_REVERSE_CASE_0 (float, /, rdiv)
> +DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_0_WRAP (float), min)
> +DEF_VF_BINOP_CASE_2_WRAP (float, MIN_FUNC_1_WRAP (float), min)
>
> /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
> /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
> @@ -33,3 +35,4 @@ DEF_VF_BINOP_REVERSE_CASE_0 (float, /, rdiv)
> /* { dg-final { scan-assembler-times {vfwnmsac.vf} 1 } } */
> /* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
> /* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
> +/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
> diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
> index 1664ac7dbce..b36e966c21c 100644
> --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
> +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-1-f64.c
> @@ -14,6 +14,8 @@ DEF_VF_MULOP_ACC_CASE_0 (double, +, -, nacc)
> DEF_VF_MULOP_ACC_CASE_0 (double, -, -, nsac)
> DEF_VF_BINOP_CASE_0 (double, *, mul)
> DEF_VF_BINOP_REVERSE_CASE_0 (double, /, rdiv)
> +DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_0_WRAP (double), min)
> +DEF_VF_BINOP_CASE_2_WRAP (double, MIN_FUNC_1_WRAP (double), min)
>
> /* { dg-final { scan-assembler-times {vfmadd.vf} 1 } } */
> /* { dg-final { scan-assembler-times {vfmsub.vf} 1 } } */
> @@ -25,3 +27,4 @@ DEF_VF_BINOP_REVERSE_CASE_0 (double, /, rdiv)
> /* { dg-final { scan-assembler-times {vfnmsac.vf} 1 } } */
> /* { dg-final { scan-assembler-times {vfmul.vf} 1 } } */
> /* { dg-final { scan-assembler-times {vfrdiv.vf} 1 } } */
> +/* { dg-final { scan-assembler-times {vfmin.vf} 2 } } */
> diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
> index 7d251c032b4..1914b18643c 100644
> --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
> +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f16.c
> @@ -17,5 +17,5 @@
> /* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
> /* { dg-final { scan-assembler-not {vfmul.vf} } } */
> /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
> +/* { dg-final { scan-assembler-not {vfmin.vf} } } */
> /* { dg-final { scan-assembler-times {fcvt.s.h} 4 } } */
> -/* { dg-final { scan-assembler-times {vfmv.v.f} 14 } } */
> diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
> index 10aac1f8745..f8dab374962 100644
> --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
> +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f32.c
> @@ -17,5 +17,5 @@
> /* { dg-final { scan-assembler-not {vfwnmsac.vf} } } */
> /* { dg-final { scan-assembler-not {vfmul.vf} } } */
> /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
> +/* { dg-final { scan-assembler-not {vfmin.vf} } } */
> /* { dg-final { scan-assembler-times {fcvt.d.s} 4 } } */
> -/* { dg-final { scan-assembler-times {vfmv.v.f} 14 } } */
> diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
> index b10261f077d..909770f7071 100644
> --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
> +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-2-f64.c
> @@ -13,3 +13,4 @@
> /* { dg-final { scan-assembler-not {vfnmsac.vf} } } */
> /* { dg-final { scan-assembler-not {vfmul.vf} } } */
> /* { dg-final { scan-assembler-not {vfrdiv.vf} } } */
> +/* { dg-final { scan-assembler-not {vfmin.vf} } } */
> diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
> index 09940e9af4a..c703ed67860 100644
> --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
> +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f16.c
> @@ -18,6 +18,10 @@ DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, +, -, nacc)
> DEF_VF_MULOP_WIDEN_CASE_1 (_Float16, float, -, -, nsac)
> DEF_VF_BINOP_CASE_1 (_Float16, *, mul, VF_BINOP_BODY_X128)
> DEF_VF_BINOP_REVERSE_CASE_1 (_Float16, /, rdiv,
> VF_BINOP_REVERSE_BODY_X128)
> +DEF_VF_BINOP_CASE_3_WRAP (_Float16, MIN_FUNC_0_WRAP (_Float16), min,
> + VF_BINOP_FUNC_BODY_X128)
> +DEF_VF_BINOP_CASE_3_WRAP (_Float16, MIN_FUNC_1_WRAP (_Float16), min,
> + VF_BINOP_FUNC_BODY_X128)
>
> /* { dg-final { scan-assembler {vfmadd.vf} } } */
> /* { dg-final { scan-assembler {vfmsub.vf} } } */
> @@ -33,3 +37,4 @@ DEF_VF_BINOP_REVERSE_CASE_1 (_Float16, /, rdiv,
> VF_BINOP_REVERSE_BODY_X128)
> /* { dg-final { scan-assembler {vfwnmsac.vf} } } */
> /* { dg-final { scan-assembler {vfmul.vf} } } */
> /* { dg-final { scan-assembler {vfrdiv.vf} } } */
> +/* { dg-final { scan-assembler {vfmin.vf} } } */
> diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
> index 42adaefe0e7..99b84dd681b 100644
> --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
> +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f32.c
> @@ -18,6 +18,10 @@ DEF_VF_MULOP_WIDEN_CASE_1 (float, double, +, -, nacc)
> DEF_VF_MULOP_WIDEN_CASE_1 (float, double, -, -, nsac)
> DEF_VF_BINOP_CASE_1 (float, *, mul, VF_BINOP_BODY_X128)
> DEF_VF_BINOP_REVERSE_CASE_1 (float, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
> +DEF_VF_BINOP_CASE_3_WRAP (float, MIN_FUNC_0_WRAP (float), min,
> + VF_BINOP_FUNC_BODY_X128)
> +DEF_VF_BINOP_CASE_3_WRAP (float, MIN_FUNC_1_WRAP (float), min,
> + VF_BINOP_FUNC_BODY_X128)
>
> /* { dg-final { scan-assembler {vfmadd.vf} } } */
> /* { dg-final { scan-assembler {vfmsub.vf} } } */
> @@ -33,3 +37,4 @@ DEF_VF_BINOP_REVERSE_CASE_1 (float, /, rdiv,
> VF_BINOP_REVERSE_BODY_X128)
> /* { dg-final { scan-assembler {vfwnmsac.vf} } } */
> /* { dg-final { scan-assembler {vfmul.vf} } } */
> /* { dg-final { scan-assembler {vfrdiv.vf} } } */
> +/* { dg-final { scan-assembler {vfmin.vf} } } */
> diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
> index 021296984bb..889fed2c83a 100644
> --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
> +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf-3-f64.c
> @@ -14,6 +14,10 @@ DEF_VF_MULOP_ACC_CASE_1 (double, +, -, nacc,
> VF_MULOP_ACC_BODY_X128)
> DEF_VF_MULOP_ACC_CASE_1 (double, -, -, nsac, VF_MULOP_ACC_BODY_X128)
> DEF_VF_BINOP_CASE_1 (double, *, mul, VF_BINOP_BODY_X128)
> DEF_VF_BINOP_REVERSE_CASE_1 (double, /, rdiv, VF_BINOP_REVERSE_BODY_X128)
> +DEF_VF_BINOP_CASE_3_WRAP (double, MIN_FUNC_0_WRAP (double), min,
> + VF_BINOP_FUNC_BODY_X128)
> +DEF_VF_BINOP_CASE_3_WRAP (double, MIN_FUNC_1_WRAP (double), min,
> + VF_BINOP_FUNC_BODY_X128)
>
> /* { dg-final { scan-assembler {vfmadd.vf} } } */
> /* { dg-final { scan-assembler {vfmsub.vf} } } */
> @@ -25,3 +29,4 @@ DEF_VF_BINOP_REVERSE_CASE_1 (double, /, rdiv,
> VF_BINOP_REVERSE_BODY_X128)
> /* { dg-final { scan-assembler {vfnmsac.vf} } } */
> /* { dg-final { scan-assembler {vfmul.vf} } } */
> /* { dg-final { scan-assembler {vfrdiv.vf} } } */
> +/* { dg-final { scan-assembler {vfmin.vf} } } */
> diff --git gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
> index b43b7dc5a97..90436a298c2 100644
> --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
> +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop.h
> @@ -123,3 +123,84 @@
> DEF_VF_BINOP_REVERSE_CASE_1 (T, OP, NAME, BODY)
>
> #endif
> +
> +#define DEF_MIN_0(T)
> \
> + static inline T test_##T##_min_0 (T a, T b) { return a > b ? b : a; }
> +
> +#define DEF_MIN_1(T)
> \
> + static inline T test_##T##_min_1 (T a, T b) { return a >= b ? b : a; }
> +
> +DEF_MIN_0 (_Float16)
> +DEF_MIN_0 (float)
> +DEF_MIN_0 (double)
> +
> +DEF_MIN_1 (_Float16)
> +DEF_MIN_1 (float)
> +DEF_MIN_1 (double)
> +
> +#define MIN_FUNC_0(T) test_##T##_min_0
> +#define MIN_FUNC_0_WRAP(T) MIN_FUNC_0 (T)
> +
> +#define MIN_FUNC_1(T) test_##T##_min_1
> +#define MIN_FUNC_1_WRAP(T) MIN_FUNC_1 (T)
> +
> +#define DEF_VF_BINOP_CASE_2(T, FUNC, NAME)
> \
> + void test_vf_binop_##NAME##_##FUNC##_##T##_case_2 (T *restrict out,
> \
> + T *restrict in, T f,
> \
> + unsigned n)
> \
> + {
> \
> + for (unsigned i = 0; i < n; i++)
> \
> + out[i] = FUNC (in[i], f);
> \
> + }
> +#define DEF_VF_BINOP_CASE_2_WRAP(T, FUNC, NAME)
> \
> + DEF_VF_BINOP_CASE_2 (T, FUNC, NAME)
> +#define RUN_VF_BINOP_CASE_2(T, NAME, FUNC, out, in, f, n)
> \
> + test_vf_binop_##NAME##_##FUNC##_##T##_case_2 (out, in, f, n)
> +#define RUN_VF_BINOP_CASE_2_WRAP(T, NAME, FUNC, out, in, f, n)
> \
> + RUN_VF_BINOP_CASE_2 (T, NAME, FUNC, out, in, f, n)
> +
> +#define DEF_VF_BINOP_CASE_3(T, FUNC, NAME, BODY)
> \
> + void test_vf_binop_##NAME##_##FUNC##_##T##_case_3 (T *restrict out,
> \
> + T *restrict in, T f,
> \
> + unsigned n)
> \
> + {
> \
> + unsigned k = 0;
> \
> + T tmp = f + 3;
> \
> +
> \
> + while (k < n)
> \
> + {
> \
> + tmp = tmp * 0x7.ap3;
> \
> + BODY (FUNC)
> \
> + }
> \
> + }
> +#define DEF_VF_BINOP_CASE_3_WRAP(T, FUNC, NAME, BODY)
> \
> + DEF_VF_BINOP_CASE_3 (T, FUNC, NAME, BODY)
> +
> +#define VF_BINOP_FUNC_BODY(func)
> \
> + out[k + 0] = func (in[k + 0], tmp);
> \
> + out[k + 1] = func (in[k + 1], tmp);
> \
> + k += 2;
> +
> +#define VF_BINOP_FUNC_BODY_X4(op)
> \
> + VF_BINOP_FUNC_BODY (op)
> \
> + VF_BINOP_FUNC_BODY (op)
> +
> +#define VF_BINOP_FUNC_BODY_X8(op)
> \
> + VF_BINOP_FUNC_BODY_X4 (op)
> \
> + VF_BINOP_FUNC_BODY_X4 (op)
> +
> +#define VF_BINOP_FUNC_BODY_X16(op)
> \
> + VF_BINOP_FUNC_BODY_X8 (op)
> \
> + VF_BINOP_FUNC_BODY_X8 (op)
> +
> +#define VF_BINOP_FUNC_BODY_X32(op)
> \
> + VF_BINOP_FUNC_BODY_X16 (op)
> \
> + VF_BINOP_FUNC_BODY_X16 (op)
> +
> +#define VF_BINOP_FUNC_BODY_X64(op)
> \
> + VF_BINOP_FUNC_BODY_X32 (op)
> \
> + VF_BINOP_FUNC_BODY_X32 (op)
> +
> +#define VF_BINOP_FUNC_BODY_X128(op)
> \
> + VF_BINOP_FUNC_BODY_X64 (op)
> \
> + VF_BINOP_FUNC_BODY_X64 (op)
> diff --git
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
> index fb902798bf7..e6ddd1ebb4f 100644
> --- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
> +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_binop_data.h
> @@ -301,4 +301,151 @@ double TEST_BINOP_DATA(double, rdiv)[][4][N] =
> },
> };
>
> +_Float16 TEST_BINOP_DATA(_Float16, min)[][4][N] =
> +{
> + {
> + { 0x1.0000000000000p+0f16 },
> + {
> + 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16,
> 0x1.8fc0000000000p+4f16, 0x1.8fc0000000000p+4f16,
> + 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16,
> 0x1.b880000000000p+6f16, 0x1.b880000000000p+6f16,
> + 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16,
> 0x1.a4c0000000000p+5f16, 0x1.a4c0000000000p+5f16,
> + 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16,
> 0x1.6f80000000000p+4f16, 0x1.6f80000000000p+4f16,
> + },
> + {
> + 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16,
> 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16,
> + 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16,
> 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16,
> + 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16,
> 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16,
> + 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16,
> 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16,
> + },
> + },
> + {
> + { 0x1.0000000000000p+0f16 },
> + {
> + -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
> -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
> + 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16,
> 0x1.c300000000000p+6f16, 0x1.c300000000000p+6f16,
> + -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
> -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
> + -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
> -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
> + },
> + {
> + -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
> -0x1.53c0000000000p+5f16, -0x1.53c0000000000p+5f16,
> + 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16,
> 0x1.0000000000000p+0f16, 0x1.0000000000000p+0f16,
> + -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
> -0x1.ffc0000000000p+7f16, -0x1.ffc0000000000p+7f16,
> + -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
> -0x1.94c0000000000p+6f16, -0x1.94c0000000000p+6f16,
> + },
> + },
> + {
> + { -0x1.0000000000000p+0f16 },
> + {
> + -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16,
> -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16,
> + -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16,
> -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16,
> + 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16,
> 0x1.96c0000000000p+4f16, 0x1.96c0000000000p+4f16,
> + -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16,
> -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16,
> + },
> + {
> + -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16,
> -0x1.0600000000000p+5f16, -0x1.0600000000000p+5f16,
> + -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16,
> -0x1.e540000000000p+7f16, -0x1.e540000000000p+7f16,
> + -0x1.0000000000000p+0f16, -0x1.0000000000000p+0f16,
> -0x1.0000000000000p+0f16, -0x1.0000000000000p+0f16,
> + -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16,
> -0x1.08c0000000000p+5f16, -0x1.08c0000000000p+5f16,
> + },
> + },
> +};
> +
> +float TEST_BINOP_DATA(float, min)[][4][N] =
> +{
> + {
> + { 0x1.0000000000000p+0f },
> + {
> + 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f,
> 0x1.8fe1540000000p+60f, 0x1.8fe1540000000p+60f,
> + 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f,
> 0x1.b8b5320000000p+62f, 0x1.b8b5320000000p+62f,
> + 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f,
> 0x1.a4eb340000000p+61f, 0x1.a4eb340000000p+61f,
> + 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f,
> 0x1.6faeda0000000p+60f, 0x1.6faeda0000000p+60f,
> + },
> + {
> + 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f,
> 0x1.0000000000000p+0f,
> + 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f,
> 0x1.0000000000000p+0f,
> + 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f,
> 0x1.0000000000000p+0f,
> + 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f,
> 0x1.0000000000000p+0f,
> + },
> + },
> + {
> + { 0x1.0000000000000p+0f },
> + {
> + -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f,
> -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f,
> + 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f,
> 0x1.c3397c0000000p+62f, 0x1.c3397c0000000p+62f,
> + -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f,
> -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f,
> + -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f,
> -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f,
> + },
> + {
> + -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f,
> -0x1.53e0ba0000000p+61f, -0x1.53e0ba0000000p+61f,
> + 0x1.0000000000000p+0f, 0x1.0000000000000p+0f, 0x1.0000000000000p+0f,
> 0x1.0000000000000p+0f,
> + -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f,
> -0x1.ffe2020000000p+63f, -0x1.ffe2020000000p+63f,
> + -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f,
> -0x1.94d2a80000000p+62f, -0x1.94d2a80000000p+62f,
> + },
> + },
> + {
> + { -0x1.bc16d60000000p+59f },
> + {
> + -0x1.062a340000000p+61f, -0x1.062a340000000p+61f,
> -0x1.062a340000000p+61f, -0x1.062a340000000p+61f,
> + -0x1.e573960000000p+63f, -0x1.e573960000000p+63f,
> -0x1.e573960000000p+63f, -0x1.e573960000000p+63f,
> + 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f,
> 0x1.96d5c20000000p+60f, 0x1.96d5c20000000p+60f,
> + -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f,
> -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f,
> + },
> + {
> + -0x1.062a340000000p+61f, -0x1.062a340000000p+61f,
> -0x1.062a340000000p+61f, -0x1.062a340000000p+61f,
> + -0x1.e573960000000p+63f, -0x1.e573960000000p+63f,
> -0x1.e573960000000p+63f, -0x1.e573960000000p+63f,
> + -0x1.bc16d60000000p+59f, -0x1.bc16d60000000p+59f,
> -0x1.bc16d60000000p+59f, -0x1.bc16d60000000p+59f,
> + -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f,
> -0x1.08eb620000000p+61f, -0x1.08eb620000000p+61f,
> + },
> + },
> +};
> +
> +double TEST_BINOP_DATA(double, min)[][4][N] =
> +{
> + {
> + { 0x1.0000000000000p+0 },
> + {
> + 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508,
> 0x1.8fe1565f12a78p+508, 0x1.8fe1565f12a78p+508,
> + 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510,
> 0x1.b8b533d821ccap+510, 0x1.b8b533d821ccap+510,
> + 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509,
> 0x1.a4eb35b744a54p+509, 0x1.a4eb35b744a54p+509,
> + 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508,
> 0x1.6faedb6395f48p+508, 0x1.6faedb6395f48p+508,
> + },
> + {
> + 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0,
> 0x1.0000000000000p+0,
> + 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0,
> 0x1.0000000000000p+0,
> + 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0,
> 0x1.0000000000000p+0,
> + 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0,
> 0x1.0000000000000p+0,
> + },
> + },
> + {
> + { 0x1.0000000000000p+0 },
> + {
> + -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509,
> -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509,
> + 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510,
> 0x1.c3397ceebc142p+510, 0x1.c3397ceebc142p+510,
> + -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511,
> -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511,
> + -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510,
> -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510,
> + },
> + {
> + -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509,
> -0x1.53e0bc0170fe8p+509, -0x1.53e0bc0170fe8p+509,
> + 0x1.0000000000000p+0, 0x1.0000000000000p+0, 0x1.0000000000000p+0,
> 0x1.0000000000000p+0,
> + -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511,
> -0x1.ffe2046f999e3p+511, -0x1.ffe2046f999e3p+511,
> + -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510,
> -0x1.94d2a9003ee18p+510, -0x1.94d2a9003ee18p+510,
> + },
> + },
> + {
> + { -0x1.317e5ef3ab327p+508 },
> + {
> + -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509,
> -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509,
> + -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511,
> -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511,
> + 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508,
> 0x1.96d5c3ca79e38p+508, 0x1.96d5c3ca79e38p+508,
> + -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509,
> -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509,
> + },
> + {
> + -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509,
> -0x1.062a35a13cec0p+509, -0x1.062a35a13cec0p+509,
> + -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511,
> -0x1.e5739808c344dp+511, -0x1.e5739808c344dp+511,
> + -0x1.317e5ef3ab327p+508, -0x1.317e5ef3ab327p+508,
> -0x1.317e5ef3ab327p+508, -0x1.317e5ef3ab327p+508,
> + -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509,
> -0x1.08eb6307cef78p+509, -0x1.08eb6307cef78p+509,
> + },
> + },
> +};
> +
> #endif
> diff --git
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c
> new file mode 100644
> index 00000000000..c84c77348ea
> --- /dev/null
> +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f16.c
> @@ -0,0 +1,20 @@
> +/* { dg-do run { target { riscv_v } } } */
> +/* { dg-require-effective-target riscv_v_ok } */
> +/* { dg-require-effective-target riscv_zvfh_ok } */
> +/* { dg-add-options "riscv_v" } */
> +/* { dg-add-options "riscv_zvfh" } */
> +/* { dg-additional-options "--param=fpr2vr-cost=0" } */
> +
> +#include "vf_binop.h"
> +#include "vf_binop_data.h"
> +
> +#define T _Float16
> +#define FUNC MIN_FUNC_0_WRAP(T)
> +#define NAME min
> +
> +DEF_VF_BINOP_CASE_2_WRAP (T, FUNC, NAME)
> +
> +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
> +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_2_WRAP(T,
> NAME, FUNC, out, in, f, n)
> +
> +#include "vf_binop_run.h"
> diff --git
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c
> new file mode 100644
> index 00000000000..a2d024e24f7
> --- /dev/null
> +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f32.c
> @@ -0,0 +1,16 @@
> +/* { dg-do run { target { riscv_v } } } */
> +/* { dg-additional-options "--param=fpr2vr-cost=0" } */
> +
> +#include "vf_binop.h"
> +#include "vf_binop_data.h"
> +
> +#define T float
> +#define FUNC MIN_FUNC_0_WRAP(T)
> +#define NAME min
> +
> +DEF_VF_BINOP_CASE_2_WRAP (T, FUNC, NAME)
> +
> +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
> +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_2_WRAP(T,
> NAME, FUNC, out, in, f, n)
> +
> +#include "vf_binop_run.h"
> diff --git
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c
> gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c
> new file mode 100644
> index 00000000000..9a66f18bc83
> --- /dev/null
> +++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmin-run-1-f64.c
> @@ -0,0 +1,16 @@
> +/* { dg-do run { target { riscv_v } } } */
> +/* { dg-additional-options "--param=fpr2vr-cost=0" } */
> +
> +#include "vf_binop.h"
> +#include "vf_binop_data.h"
> +
> +#define T double
> +#define FUNC MIN_FUNC_0_WRAP(T)
> +#define NAME min
> +
> +DEF_VF_BINOP_CASE_2_WRAP (T, FUNC, NAME)
> +
> +#define TEST_DATA TEST_BINOP_DATA_WRAP(T, NAME)
> +#define TEST_RUN(T, NAME, out, in, f, n) RUN_VF_BINOP_CASE_2_WRAP(T,
> NAME, FUNC, out, in, f, n)
> +
> +#include "vf_binop_run.h"
> --
> 2.39.5
>
>
