claudiu.zissulescu-iancule...@oracle.com writes:
> From: Claudiu Zissulescu <claudiu.zissulescu-iancule...@oracle.com>
>
> Add a new target instruction. Hardware-assisted sanitizers on
> architectures providing insstructions to tag/untag memory can then
> make use of this new instruction pattern. For example, the
> memtag-stack sanitizer uses these instructions to tag and untag a
> memory granule.
>
> gcc/doc/
>
> * md.texi (tag_memory): Add documentation.
>
> gcc/
>
> * target-insns.def (tag_memory): New target instruction.
>
> Signed-off-by: Claudiu Zissulescu <claudiu.zissulescu-iancule...@oracle.com>
> ---
> gcc/doc/md.texi | 5 +++++
> gcc/target-insns.def | 1 +
> 2 files changed, 6 insertions(+)
>
> diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
> index 28159b2e820..e4c9a472e3f 100644
> --- a/gcc/doc/md.texi
> +++ b/gcc/doc/md.texi
> @@ -8578,6 +8578,11 @@ the values were equal.
> If this pattern is not defined, then a plain compare pattern and
> conditional branch pattern is used.
>
> +@cindex @code{tag_memory} instruction pattern
> +This pattern tags an object that begins at the address specified by
> +operand 0, has the size indicated by the operand 2, and uses the tag
Might be worth saying "byte size" instead of just "size".
OK with that change, thanks.
Richard
> +from operand 1.
> +
> @cindex @code{clear_cache} instruction pattern
> @item @samp{clear_cache}
> This pattern, if defined, flushes the instruction cache for a region of
> diff --git a/gcc/target-insns.def b/gcc/target-insns.def
> index 59025a20bf7..16e1d8cf565 100644
> --- a/gcc/target-insns.def
> +++ b/gcc/target-insns.def
> @@ -102,6 +102,7 @@ DEF_TARGET_INSN (stack_protect_combined_test, (rtx x0,
> rtx x1, rtx x2))
> DEF_TARGET_INSN (stack_protect_test, (rtx x0, rtx x1, rtx x2))
> DEF_TARGET_INSN (store_multiple, (rtx x0, rtx x1, rtx x2))
> DEF_TARGET_INSN (tablejump, (rtx x0, rtx x1))
> +DEF_TARGET_INSN (tag_memory, (rtx x0, rtx x1, rtx x2))
> DEF_TARGET_INSN (trap, (void))
> DEF_TARGET_INSN (unique, (void))
> DEF_TARGET_INSN (untyped_call, (rtx x0, rtx x1, rtx x2))
