The MIPS Allegrex CPU is based on MIPS2 with some additional MIPS32r2
instructions and a few novel ones. Support for this CPU was added as of
binutils 2.41.

gcc/ChangeLog:

        * config/mips/mips-cpus.def (MIPS_CPU): Added a new CPU.
        * config/mips/mips-tables.opt: Regenerated table.
        * config/mips/mips.cc: Added cost table for the new CPU.
        * config/mips/mips.h (TARGET_ALLEGREX): Defined a new macro.
        (TUNE_ALLEGREX): Defined a new macro.
        (ISA_HAS_CONDMOVE): Added Allegrex CPU to the list.
        (ISA_HAS_LDC1_SDC1): Exclude Allegrex from the list.
        (ISA_HAS_COND_TRAP): Exclude Allegrex from the list.
        (ISA_HAS_COND_TRAPI): Exclude Allegrex from the list.
        (ISA_HAS_CLZ_CLO): Added Allegrex CPU to the list.
        (ISA_HAS_ROR): Added Allegrex CPU to the list.
        (ISA_HAS_WSBH): Added Allegrex CPU to the list.
        (ISA_HAS_SEB_SEH): Added Allegrex CPU to the list.
        (ISA_HAS_EXT_INS): Added Allegrex CPU to the list.
        (ISA_HAS_XFER_DELAY): Exclude Allegrex from the list.
        (ISA_HAS_HILO_INTERLOCKS): Added Allegrex CPU to the list.
        * config/mips/mips.md: Added Allegrex CPU as a new processor.
        * doc/invoke.texi: Documented Allegrex as a new arch

Signed-off-by: David Guillen Fandos <da...@davidgf.net>
---
 gcc/config/mips/mips-cpus.def   |   1 +
 gcc/config/mips/mips-tables.opt | 371 ++++++++++++++++----------------
 gcc/config/mips/mips.cc         |  14 ++
 gcc/config/mips/mips.h          |  21 +-
 gcc/config/mips/mips.md         |   3 +
 gcc/doc/invoke.texi             |   1 +
 6 files changed, 223 insertions(+), 188 deletions(-)

diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def
index dfc41162bf0..c45da84a77a 100644
--- a/gcc/config/mips/mips-cpus.def
+++ b/gcc/config/mips/mips-cpus.def
@@ -62,6 +62,7 @@ MIPS_CPU ("r3900", PROCESSOR_R3900, MIPS_ISA_MIPS1, 0)
 
 /* MIPS II processors.  */
 MIPS_CPU ("r6000", PROCESSOR_R6000, MIPS_ISA_MIPS2, 0)
+MIPS_CPU ("allegrex", PROCESSOR_ALLEGREX, MIPS_ISA_MIPS2, 0)
 
 /* MIPS III processors.  */
 MIPS_CPU ("r4000", PROCESSOR_R4000, MIPS_ISA_MIPS3, 0)
diff --git a/gcc/config/mips/mips-tables.opt b/gcc/config/mips/mips-tables.opt
index 027abd74048..5fccd9888b7 100644
--- a/gcc/config/mips/mips-tables.opt
+++ b/gcc/config/mips/mips-tables.opt
@@ -160,554 +160,557 @@ EnumValue
 Enum(mips_arch_opt_value) String(6k) Value(17)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4000) Value(18) Canonical
+Enum(mips_arch_opt_value) String(allegrex) Value(18) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4k) Value(18)
+Enum(mips_arch_opt_value) String(r4000) Value(19) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(4000) Value(18)
+Enum(mips_arch_opt_value) String(r4k) Value(19)
 
 EnumValue
-Enum(mips_arch_opt_value) String(4k) Value(18)
+Enum(mips_arch_opt_value) String(4000) Value(19)
 
 EnumValue
-Enum(mips_arch_opt_value) String(vr4100) Value(19) Canonical
+Enum(mips_arch_opt_value) String(4k) Value(19)
 
 EnumValue
-Enum(mips_arch_opt_value) String(4100) Value(19)
+Enum(mips_arch_opt_value) String(vr4100) Value(20) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4100) Value(19)
+Enum(mips_arch_opt_value) String(4100) Value(20)
 
 EnumValue
-Enum(mips_arch_opt_value) String(vr4111) Value(20) Canonical
+Enum(mips_arch_opt_value) String(r4100) Value(20)
 
 EnumValue
-Enum(mips_arch_opt_value) String(4111) Value(20)
+Enum(mips_arch_opt_value) String(vr4111) Value(21) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4111) Value(20)
+Enum(mips_arch_opt_value) String(4111) Value(21)
 
 EnumValue
-Enum(mips_arch_opt_value) String(vr4120) Value(21) Canonical
+Enum(mips_arch_opt_value) String(r4111) Value(21)
 
 EnumValue
-Enum(mips_arch_opt_value) String(4120) Value(21)
+Enum(mips_arch_opt_value) String(vr4120) Value(22) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4120) Value(21)
+Enum(mips_arch_opt_value) String(4120) Value(22)
 
 EnumValue
-Enum(mips_arch_opt_value) String(vr4130) Value(22) Canonical
+Enum(mips_arch_opt_value) String(r4120) Value(22)
 
 EnumValue
-Enum(mips_arch_opt_value) String(4130) Value(22)
+Enum(mips_arch_opt_value) String(vr4130) Value(23) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4130) Value(22)
+Enum(mips_arch_opt_value) String(4130) Value(23)
 
 EnumValue
-Enum(mips_arch_opt_value) String(vr4300) Value(23) Canonical
+Enum(mips_arch_opt_value) String(r4130) Value(23)
 
 EnumValue
-Enum(mips_arch_opt_value) String(4300) Value(23)
+Enum(mips_arch_opt_value) String(vr4300) Value(24) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4300) Value(23)
+Enum(mips_arch_opt_value) String(4300) Value(24)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4400) Value(24) Canonical
+Enum(mips_arch_opt_value) String(r4300) Value(24)
 
 EnumValue
-Enum(mips_arch_opt_value) String(4400) Value(24)
+Enum(mips_arch_opt_value) String(r4400) Value(25) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4600) Value(25) Canonical
+Enum(mips_arch_opt_value) String(4400) Value(25)
 
 EnumValue
-Enum(mips_arch_opt_value) String(4600) Value(25)
+Enum(mips_arch_opt_value) String(r4600) Value(26) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(orion) Value(26) Canonical
+Enum(mips_arch_opt_value) String(4600) Value(26)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4650) Value(27) Canonical
+Enum(mips_arch_opt_value) String(orion) Value(27) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(4650) Value(27)
+Enum(mips_arch_opt_value) String(r4650) Value(28) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4700) Value(28) Canonical
+Enum(mips_arch_opt_value) String(4650) Value(28)
 
 EnumValue
-Enum(mips_arch_opt_value) String(4700) Value(28)
+Enum(mips_arch_opt_value) String(r4700) Value(29) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(r5900) Value(29) Canonical
+Enum(mips_arch_opt_value) String(4700) Value(29)
 
 EnumValue
-Enum(mips_arch_opt_value) String(5900) Value(29)
+Enum(mips_arch_opt_value) String(r5900) Value(30) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(loongson2e) Value(30) Canonical
+Enum(mips_arch_opt_value) String(5900) Value(30)
 
 EnumValue
-Enum(mips_arch_opt_value) String(loongson2f) Value(31) Canonical
+Enum(mips_arch_opt_value) String(loongson2e) Value(31) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(r8000) Value(32) Canonical
+Enum(mips_arch_opt_value) String(loongson2f) Value(32) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(r8k) Value(32)
+Enum(mips_arch_opt_value) String(r8000) Value(33) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(8000) Value(32)
+Enum(mips_arch_opt_value) String(r8k) Value(33)
 
 EnumValue
-Enum(mips_arch_opt_value) String(8k) Value(32)
+Enum(mips_arch_opt_value) String(8000) Value(33)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r10000) Value(33) Canonical
+Enum(mips_arch_opt_value) String(8k) Value(33)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r10k) Value(33)
+Enum(mips_arch_opt_value) String(r10000) Value(34) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(10000) Value(33)
+Enum(mips_arch_opt_value) String(r10k) Value(34)
 
 EnumValue
-Enum(mips_arch_opt_value) String(10k) Value(33)
+Enum(mips_arch_opt_value) String(10000) Value(34)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r12000) Value(34) Canonical
+Enum(mips_arch_opt_value) String(10k) Value(34)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r12k) Value(34)
+Enum(mips_arch_opt_value) String(r12000) Value(35) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(12000) Value(34)
+Enum(mips_arch_opt_value) String(r12k) Value(35)
 
 EnumValue
-Enum(mips_arch_opt_value) String(12k) Value(34)
+Enum(mips_arch_opt_value) String(12000) Value(35)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r14000) Value(35) Canonical
+Enum(mips_arch_opt_value) String(12k) Value(35)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r14k) Value(35)
+Enum(mips_arch_opt_value) String(r14000) Value(36) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(14000) Value(35)
+Enum(mips_arch_opt_value) String(r14k) Value(36)
 
 EnumValue
-Enum(mips_arch_opt_value) String(14k) Value(35)
+Enum(mips_arch_opt_value) String(14000) Value(36)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r16000) Value(36) Canonical
+Enum(mips_arch_opt_value) String(14k) Value(36)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r16k) Value(36)
+Enum(mips_arch_opt_value) String(r16000) Value(37) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(16000) Value(36)
+Enum(mips_arch_opt_value) String(r16k) Value(37)
 
 EnumValue
-Enum(mips_arch_opt_value) String(16k) Value(36)
+Enum(mips_arch_opt_value) String(16000) Value(37)
 
 EnumValue
-Enum(mips_arch_opt_value) String(vr5000) Value(37) Canonical
+Enum(mips_arch_opt_value) String(16k) Value(37)
 
 EnumValue
-Enum(mips_arch_opt_value) String(vr5k) Value(37)
+Enum(mips_arch_opt_value) String(vr5000) Value(38) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(5000) Value(37)
+Enum(mips_arch_opt_value) String(vr5k) Value(38)
 
 EnumValue
-Enum(mips_arch_opt_value) String(5k) Value(37)
+Enum(mips_arch_opt_value) String(5000) Value(38)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r5000) Value(37)
+Enum(mips_arch_opt_value) String(5k) Value(38)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r5k) Value(37)
+Enum(mips_arch_opt_value) String(r5000) Value(38)
 
 EnumValue
-Enum(mips_arch_opt_value) String(vr5400) Value(38) Canonical
+Enum(mips_arch_opt_value) String(r5k) Value(38)
 
 EnumValue
-Enum(mips_arch_opt_value) String(5400) Value(38)
+Enum(mips_arch_opt_value) String(vr5400) Value(39) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(r5400) Value(38)
+Enum(mips_arch_opt_value) String(5400) Value(39)
 
 EnumValue
-Enum(mips_arch_opt_value) String(vr5500) Value(39) Canonical
+Enum(mips_arch_opt_value) String(r5400) Value(39)
 
 EnumValue
-Enum(mips_arch_opt_value) String(5500) Value(39)
+Enum(mips_arch_opt_value) String(vr5500) Value(40) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(r5500) Value(39)
+Enum(mips_arch_opt_value) String(5500) Value(40)
 
 EnumValue
-Enum(mips_arch_opt_value) String(rm7000) Value(40) Canonical
+Enum(mips_arch_opt_value) String(r5500) Value(40)
 
 EnumValue
-Enum(mips_arch_opt_value) String(rm7k) Value(40)
+Enum(mips_arch_opt_value) String(rm7000) Value(41) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(7000) Value(40)
+Enum(mips_arch_opt_value) String(rm7k) Value(41)
 
 EnumValue
-Enum(mips_arch_opt_value) String(7k) Value(40)
+Enum(mips_arch_opt_value) String(7000) Value(41)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r7000) Value(40)
+Enum(mips_arch_opt_value) String(7k) Value(41)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r7k) Value(40)
+Enum(mips_arch_opt_value) String(r7000) Value(41)
 
 EnumValue
-Enum(mips_arch_opt_value) String(rm9000) Value(41) Canonical
+Enum(mips_arch_opt_value) String(r7k) Value(41)
 
 EnumValue
-Enum(mips_arch_opt_value) String(rm9k) Value(41)
+Enum(mips_arch_opt_value) String(rm9000) Value(42) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(9000) Value(41)
+Enum(mips_arch_opt_value) String(rm9k) Value(42)
 
 EnumValue
-Enum(mips_arch_opt_value) String(9k) Value(41)
+Enum(mips_arch_opt_value) String(9000) Value(42)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r9000) Value(41)
+Enum(mips_arch_opt_value) String(9k) Value(42)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r9k) Value(41)
+Enum(mips_arch_opt_value) String(r9000) Value(42)
 
 EnumValue
-Enum(mips_arch_opt_value) String(4kc) Value(42) Canonical
+Enum(mips_arch_opt_value) String(r9k) Value(42)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4kc) Value(42)
+Enum(mips_arch_opt_value) String(4kc) Value(43) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(4km) Value(43) Canonical
+Enum(mips_arch_opt_value) String(r4kc) Value(43)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4km) Value(43)
+Enum(mips_arch_opt_value) String(4km) Value(44) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(4kp) Value(44) Canonical
+Enum(mips_arch_opt_value) String(r4km) Value(44)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4kp) Value(44)
+Enum(mips_arch_opt_value) String(4kp) Value(45) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(4ksc) Value(45) Canonical
+Enum(mips_arch_opt_value) String(r4kp) Value(45)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4ksc) Value(45)
+Enum(mips_arch_opt_value) String(4ksc) Value(46) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(m4k) Value(46) Canonical
+Enum(mips_arch_opt_value) String(r4ksc) Value(46)
 
 EnumValue
-Enum(mips_arch_opt_value) String(m14kc) Value(47) Canonical
+Enum(mips_arch_opt_value) String(m4k) Value(47) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(m14k) Value(48) Canonical
+Enum(mips_arch_opt_value) String(m14kc) Value(48) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(m14ke) Value(49) Canonical
+Enum(mips_arch_opt_value) String(m14k) Value(49) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(m14kec) Value(50) Canonical
+Enum(mips_arch_opt_value) String(m14ke) Value(50) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(4kec) Value(51) Canonical
+Enum(mips_arch_opt_value) String(m14kec) Value(51) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4kec) Value(51)
+Enum(mips_arch_opt_value) String(4kec) Value(52) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(4kem) Value(52) Canonical
+Enum(mips_arch_opt_value) String(r4kec) Value(52)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4kem) Value(52)
+Enum(mips_arch_opt_value) String(4kem) Value(53) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(4kep) Value(53) Canonical
+Enum(mips_arch_opt_value) String(r4kem) Value(53)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4kep) Value(53)
+Enum(mips_arch_opt_value) String(4kep) Value(54) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(4ksd) Value(54) Canonical
+Enum(mips_arch_opt_value) String(r4kep) Value(54)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r4ksd) Value(54)
+Enum(mips_arch_opt_value) String(4ksd) Value(55) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(24kc) Value(55) Canonical
+Enum(mips_arch_opt_value) String(r4ksd) Value(55)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r24kc) Value(55)
+Enum(mips_arch_opt_value) String(24kc) Value(56) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(24kf2_1) Value(56) Canonical
+Enum(mips_arch_opt_value) String(r24kc) Value(56)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r24kf2_1) Value(56)
+Enum(mips_arch_opt_value) String(24kf2_1) Value(57) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(24kf) Value(57) Canonical
+Enum(mips_arch_opt_value) String(r24kf2_1) Value(57)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r24kf) Value(57)
+Enum(mips_arch_opt_value) String(24kf) Value(58) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(24kf1_1) Value(58) Canonical
+Enum(mips_arch_opt_value) String(r24kf) Value(58)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r24kf1_1) Value(58)
+Enum(mips_arch_opt_value) String(24kf1_1) Value(59) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(24kfx) Value(59) Canonical
+Enum(mips_arch_opt_value) String(r24kf1_1) Value(59)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r24kfx) Value(59)
+Enum(mips_arch_opt_value) String(24kfx) Value(60) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(24kx) Value(60) Canonical
+Enum(mips_arch_opt_value) String(r24kfx) Value(60)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r24kx) Value(60)
+Enum(mips_arch_opt_value) String(24kx) Value(61) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(24kec) Value(61) Canonical
+Enum(mips_arch_opt_value) String(r24kx) Value(61)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r24kec) Value(61)
+Enum(mips_arch_opt_value) String(24kec) Value(62) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(24kef2_1) Value(62) Canonical
+Enum(mips_arch_opt_value) String(r24kec) Value(62)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r24kef2_1) Value(62)
+Enum(mips_arch_opt_value) String(24kef2_1) Value(63) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(24kef) Value(63) Canonical
+Enum(mips_arch_opt_value) String(r24kef2_1) Value(63)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r24kef) Value(63)
+Enum(mips_arch_opt_value) String(24kef) Value(64) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(24kef1_1) Value(64) Canonical
+Enum(mips_arch_opt_value) String(r24kef) Value(64)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r24kef1_1) Value(64)
+Enum(mips_arch_opt_value) String(24kef1_1) Value(65) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(24kefx) Value(65) Canonical
+Enum(mips_arch_opt_value) String(r24kef1_1) Value(65)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r24kefx) Value(65)
+Enum(mips_arch_opt_value) String(24kefx) Value(66) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(24kex) Value(66) Canonical
+Enum(mips_arch_opt_value) String(r24kefx) Value(66)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r24kex) Value(66)
+Enum(mips_arch_opt_value) String(24kex) Value(67) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(34kc) Value(67) Canonical
+Enum(mips_arch_opt_value) String(r24kex) Value(67)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r34kc) Value(67)
+Enum(mips_arch_opt_value) String(34kc) Value(68) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(34kf2_1) Value(68) Canonical
+Enum(mips_arch_opt_value) String(r34kc) Value(68)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r34kf2_1) Value(68)
+Enum(mips_arch_opt_value) String(34kf2_1) Value(69) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(34kf) Value(69) Canonical
+Enum(mips_arch_opt_value) String(r34kf2_1) Value(69)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r34kf) Value(69)
+Enum(mips_arch_opt_value) String(34kf) Value(70) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(34kf1_1) Value(70) Canonical
+Enum(mips_arch_opt_value) String(r34kf) Value(70)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r34kf1_1) Value(70)
+Enum(mips_arch_opt_value) String(34kf1_1) Value(71) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(34kfx) Value(71) Canonical
+Enum(mips_arch_opt_value) String(r34kf1_1) Value(71)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r34kfx) Value(71)
+Enum(mips_arch_opt_value) String(34kfx) Value(72) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(34kx) Value(72) Canonical
+Enum(mips_arch_opt_value) String(r34kfx) Value(72)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r34kx) Value(72)
+Enum(mips_arch_opt_value) String(34kx) Value(73) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(34kn) Value(73) Canonical
+Enum(mips_arch_opt_value) String(r34kx) Value(73)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r34kn) Value(73)
+Enum(mips_arch_opt_value) String(34kn) Value(74) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(74kc) Value(74) Canonical
+Enum(mips_arch_opt_value) String(r34kn) Value(74)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r74kc) Value(74)
+Enum(mips_arch_opt_value) String(74kc) Value(75) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(74kf2_1) Value(75) Canonical
+Enum(mips_arch_opt_value) String(r74kc) Value(75)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r74kf2_1) Value(75)
+Enum(mips_arch_opt_value) String(74kf2_1) Value(76) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(74kf) Value(76) Canonical
+Enum(mips_arch_opt_value) String(r74kf2_1) Value(76)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r74kf) Value(76)
+Enum(mips_arch_opt_value) String(74kf) Value(77) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(74kf1_1) Value(77) Canonical
+Enum(mips_arch_opt_value) String(r74kf) Value(77)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r74kf1_1) Value(77)
+Enum(mips_arch_opt_value) String(74kf1_1) Value(78) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(74kfx) Value(78) Canonical
+Enum(mips_arch_opt_value) String(r74kf1_1) Value(78)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r74kfx) Value(78)
+Enum(mips_arch_opt_value) String(74kfx) Value(79) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(74kx) Value(79) Canonical
+Enum(mips_arch_opt_value) String(r74kfx) Value(79)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r74kx) Value(79)
+Enum(mips_arch_opt_value) String(74kx) Value(80) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(74kf3_2) Value(80) Canonical
+Enum(mips_arch_opt_value) String(r74kx) Value(80)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r74kf3_2) Value(80)
+Enum(mips_arch_opt_value) String(74kf3_2) Value(81) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(1004kc) Value(81) Canonical
+Enum(mips_arch_opt_value) String(r74kf3_2) Value(81)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r1004kc) Value(81)
+Enum(mips_arch_opt_value) String(1004kc) Value(82) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(1004kf2_1) Value(82) Canonical
+Enum(mips_arch_opt_value) String(r1004kc) Value(82)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r1004kf2_1) Value(82)
+Enum(mips_arch_opt_value) String(1004kf2_1) Value(83) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(1004kf) Value(83) Canonical
+Enum(mips_arch_opt_value) String(r1004kf2_1) Value(83)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r1004kf) Value(83)
+Enum(mips_arch_opt_value) String(1004kf) Value(84) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(1004kf1_1) Value(84) Canonical
+Enum(mips_arch_opt_value) String(r1004kf) Value(84)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r1004kf1_1) Value(84)
+Enum(mips_arch_opt_value) String(1004kf1_1) Value(85) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(interaptiv) Value(85) Canonical
+Enum(mips_arch_opt_value) String(r1004kf1_1) Value(85)
 
 EnumValue
-Enum(mips_arch_opt_value) String(p5600) Value(86) Canonical
+Enum(mips_arch_opt_value) String(interaptiv) Value(86) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(m5100) Value(87) Canonical
+Enum(mips_arch_opt_value) String(p5600) Value(87) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(m5101) Value(88) Canonical
+Enum(mips_arch_opt_value) String(m5100) Value(88) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(5kc) Value(89) Canonical
+Enum(mips_arch_opt_value) String(m5101) Value(89) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(r5kc) Value(89)
+Enum(mips_arch_opt_value) String(5kc) Value(90) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(5kf) Value(90) Canonical
+Enum(mips_arch_opt_value) String(r5kc) Value(90)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r5kf) Value(90)
+Enum(mips_arch_opt_value) String(5kf) Value(91) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(20kc) Value(91) Canonical
+Enum(mips_arch_opt_value) String(r5kf) Value(91)
 
 EnumValue
-Enum(mips_arch_opt_value) String(r20kc) Value(91)
+Enum(mips_arch_opt_value) String(20kc) Value(92) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(sb1) Value(92) Canonical
+Enum(mips_arch_opt_value) String(r20kc) Value(92)
 
 EnumValue
-Enum(mips_arch_opt_value) String(sb1a) Value(93) Canonical
+Enum(mips_arch_opt_value) String(sb1) Value(93) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(sr71000) Value(94) Canonical
+Enum(mips_arch_opt_value) String(sb1a) Value(94) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(sr71k) Value(94)
+Enum(mips_arch_opt_value) String(sr71000) Value(95) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(xlr) Value(95) Canonical
+Enum(mips_arch_opt_value) String(sr71k) Value(95)
 
 EnumValue
-Enum(mips_arch_opt_value) String(loongson3a) Value(96) Canonical
+Enum(mips_arch_opt_value) String(xlr) Value(96) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(gs464) Value(97) Canonical
+Enum(mips_arch_opt_value) String(loongson3a) Value(97) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(gs464e) Value(98) Canonical
+Enum(mips_arch_opt_value) String(gs464) Value(98) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(gs264e) Value(99) Canonical
+Enum(mips_arch_opt_value) String(gs464e) Value(99) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(octeon) Value(100) Canonical
+Enum(mips_arch_opt_value) String(gs264e) Value(100) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(octeon+) Value(101) Canonical
+Enum(mips_arch_opt_value) String(octeon) Value(101) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(octeon2) Value(102) Canonical
+Enum(mips_arch_opt_value) String(octeon+) Value(102) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(octeon3) Value(103) Canonical
+Enum(mips_arch_opt_value) String(octeon2) Value(103) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(xlp) Value(104) Canonical
+Enum(mips_arch_opt_value) String(octeon3) Value(104) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(i6400) Value(105) Canonical
+Enum(mips_arch_opt_value) String(xlp) Value(105) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(i6500) Value(106) Canonical
+Enum(mips_arch_opt_value) String(i6400) Value(106) Canonical
 
 EnumValue
-Enum(mips_arch_opt_value) String(p6600) Value(107) Canonical
+Enum(mips_arch_opt_value) String(i6500) Value(107) Canonical
+
+EnumValue
+Enum(mips_arch_opt_value) String(p6600) Value(108) Canonical
 
diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 81eaa3cfb2a..0be9e05dbd4 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -915,6 +915,20 @@ static const struct mips_rtx_cost_data
                     2,           /* branch_cost */
                     6            /* memory_latency */
   },
+  { /* Allegrex */
+    /* Has hard-float support for single precision only. */
+    COSTS_N_INSNS (5),            /* fp_add */
+    COSTS_N_INSNS (5),            /* fp_mult_sf */
+    COSTS_N_INSNS (256),          /* fp_mult_df */
+    COSTS_N_INSNS (30),           /* fp_div_sf */
+    COSTS_N_INSNS (256),          /* fp_div_df */
+    COSTS_N_INSNS (7) ,           /* int_mult_si */
+    COSTS_N_INSNS (27),           /* int_mult_di */
+    COSTS_N_INSNS (21),           /* int_div_si */
+    COSTS_N_INSNS (256),          /* int_div_di */
+                    2,           /* branch_cost */
+                    4            /* memory_latency */
+  },
   { /* R4000 */
      COSTS_N_INSNS (6),           /* fp_add */
      COSTS_N_INSNS (7),           /* fp_mult_sf */
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index e224ade2a1a..5b224b7ae0e 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -291,6 +291,7 @@ struct mips_cpu_info {
 #define ISA_MIPS64R6               (mips_isa == MIPS_ISA_MIPS64R6)
 
 /* Architecture target defines.  */
+#define TARGET_ALLEGREX             (mips_arch == PROCESSOR_ALLEGREX)
 #define TARGET_LOONGSON_2E          (mips_arch == PROCESSOR_LOONGSON_2E)
 #define TARGET_LOONGSON_2F          (mips_arch == PROCESSOR_LOONGSON_2F)
 #define TARGET_LOONGSON_2EF         (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
@@ -326,6 +327,7 @@ struct mips_cpu_info {
                                     || mips_tune == PROCESSOR_74KF2_1  \
                                     || mips_tune == PROCESSOR_74KF1_1  \
                                     || mips_tune == PROCESSOR_74KF3_2)
+#define TUNE_ALLEGREX              (mips_tune == PROCESSOR_ALLEGREX)
 #define TUNE_LOONGSON_2EF           (mips_tune == PROCESSOR_LOONGSON_2E        
\
                                     || mips_tune == PROCESSOR_LOONGSON_2F)
 #define TUNE_GS464                 (mips_tune == PROCESSOR_GS464)
@@ -1091,12 +1093,14 @@ struct mips_cpu_info {
 /* ISA has the integer conditional move instructions introduced in mips4 and
    ST Loongson 2E/2F.  */
 #define ISA_HAS_CONDMOVE        (ISA_HAS_FP_CONDMOVE                   \
+                                || TARGET_ALLEGREX                     \
                                 || TARGET_MIPS5900                     \
                                 || ISA_HAS_MIPS16E2                    \
                                 || TARGET_LOONGSON_2EF)
 
 /* ISA has LDC1 and SDC1.  */
 #define ISA_HAS_LDC1_SDC1      (!ISA_MIPS1                             \
+                                && !TARGET_ALLEGREX                    \
                                 && !TARGET_MIPS5900                    \
                                 && !TARGET_MIPS16)
 
@@ -1135,11 +1139,13 @@ struct mips_cpu_info {
 
 /* ISA has conditional trap instructions.  */
 #define ISA_HAS_COND_TRAP      (!ISA_MIPS1                             \
+                                && !TARGET_ALLEGREX                    \
                                 && !TARGET_MIPS16)
 
 /* ISA has conditional trap with immediate instructions.  */
 #define ISA_HAS_COND_TRAPI     (!ISA_MIPS1                             \
                                 && mips_isa_rev <= 5                   \
+                                && !TARGET_ALLEGREX                    \
                                 && !TARGET_MIPS16)
 
 /* ISA has integer multiply-accumulate instructions, madd and msub.  */
@@ -1199,7 +1205,8 @@ struct mips_cpu_info {
 #define ISA_HAS_IEEE_754_2008  (mips_isa_rev >= 2)
 
 /* ISA has count leading zeroes/ones instruction (not implemented).  */
-#define ISA_HAS_CLZ_CLO                (mips_isa_rev >= 1 && !TARGET_MIPS16)
+#define ISA_HAS_CLZ_CLO                ((mips_isa_rev >= 1 && !TARGET_MIPS16)  
 \
+                                 || TARGET_ALLEGREX)
 
 /* ISA has count trailing zeroes/ones instruction.  */
 #define ISA_HAS_CTZ_CTO                (TARGET_LOONGSON_EXT2)
@@ -1241,6 +1248,7 @@ struct mips_cpu_info {
 
 /* ISA has the "ror" (rotate right) instructions.  */
 #define ISA_HAS_ROR            ((mips_isa_rev >= 2                     \
+                                 || TARGET_ALLEGREX                    \
                                  || TARGET_MIPS5400                    \
                                  || TARGET_MIPS5500                    \
                                  || TARGET_SR71K                       \
@@ -1249,7 +1257,8 @@ struct mips_cpu_info {
 
 /* ISA has the WSBH (word swap bytes within halfwords) instruction.
    64-bit targets also provide DSBH and DSHD.  */
-#define ISA_HAS_WSBH           (mips_isa_rev >= 2 && !TARGET_MIPS16)
+#define ISA_HAS_WSBH           ((mips_isa_rev >= 2 && !TARGET_MIPS16)  \
+                                 || TARGET_ALLEGREX)
 
 /* ISA has data prefetch instructions.  This controls use of 'pref'.  */
 #define ISA_HAS_PREFETCH       ((ISA_MIPS4                             \
@@ -1282,11 +1291,13 @@ struct mips_cpu_info {
 #define ISA_HAS_TRUNC_W                (!ISA_MIPS1)
 
 /* ISA includes the MIPS32r2 seb and seh instructions.  */
-#define ISA_HAS_SEB_SEH                (mips_isa_rev >= 2 && !TARGET_MIPS16)
+#define ISA_HAS_SEB_SEH                ((mips_isa_rev >= 2 && !TARGET_MIPS16)  
\
+                                 || TARGET_ALLEGREX)
 
 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions.  */
 #define ISA_HAS_EXT_INS                ((mips_isa_rev >= 2 && !TARGET_MIPS16)  
\
-                                || ISA_HAS_MIPS16E2)
+                                || ISA_HAS_MIPS16E2 \
+                                || TARGET_ALLEGREX)
 
 /* ISA has instructions for accessing top part of 64-bit fp regs.  */
 #define ISA_HAS_MXHC1          (!TARGET_FLOAT32        \
@@ -1330,6 +1341,7 @@ struct mips_cpu_info {
 
 /* Likewise mtc1 and mfc1.  */
 #define ISA_HAS_XFER_DELAY     (mips_isa <= MIPS_ISA_MIPS3     \
+                                && !TARGET_ALLEGREX            \
                                 && !TARGET_MIPS5900            \
                                 && !TARGET_LOONGSON_2EF)
 
@@ -1351,6 +1363,7 @@ struct mips_cpu_info {
    earlier-ISA CPUs for which CPU documentation declares that the
    instructions are really interlocked.  */
 #define ISA_HAS_HILO_INTERLOCKS        (mips_isa_rev >= 1                      
\
+                                || TARGET_ALLEGREX                     \
                                 || TARGET_MIPS5500                     \
                                 || TARGET_MIPS5900                     \
                                 || TARGET_LOONGSON_2EF)
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index aadf4dd676e..79155957b2f 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -46,6 +46,7 @@
   octeon3
   r3900
   r6000
+  allegrex
   r4000
   r4100
   r4111
@@ -835,9 +836,11 @@
 ;; conditional-move-type condition is needed.
 (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT")
                               (CC "TARGET_HARD_FLOAT
+                                  && !TARGET_ALLEGREX
                                   && !TARGET_LOONGSON_2EF
                                   && !TARGET_MIPS5900")
                               (CCE "TARGET_HARD_FLOAT
+                                  && !TARGET_ALLEGREX
                                   && !TARGET_LOONGSON_2EF
                                   && !TARGET_MIPS5900")])
 
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 28466c449b9..fc4c61c1922 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -29371,6 +29371,7 @@ The processor names are:
 @samp{vr4100}, @samp{vr4111}, @samp{vr4120}, @samp{vr4130}, @samp{vr4300},
 @samp{vr5000}, @samp{vr5400}, @samp{vr5500},
 @samp{xlr} and @samp{xlp}.
+@samp{allegrex},
 The special value @samp{from-abi} selects the
 most compatible architecture for the selected ABI (that is,
 @samp{mips1} for 32-bit ABIs and @samp{mips3} for 64-bit ABIs)@.
-- 
2.50.0


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