[PATCH v1 0/4] RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2VR cost

[pan2 . li]

From: Pan Li <pan2...@intel.com>

This patch would like to introduce the combine of vec_dup + vaadd.vv
into vaadd.vx on the cost value of GR2VR.  The late-combine will take
place if the cost of GR2VR is zero, or reject the combine if non-zero
like 1, 2, 15 in test.  There will be two cases for the combine:

Case 0:
 |   ...
 |   vmv.v.x
 | L1:
 |   vaadd.vv
 |   J L1
 |   ...

Case 1:
 |   ...
 | L1:
 |   vmv.v.x
 |   vaadd.vv
 |   J L1
 |   ...

Both will be combined to below if the cost of GR2VR is zero.
 |   ...
 | L1:
 |   vaadd.vx
 |   J L1
 |   ...

The below test suites are passed for this patch series.
* The rv64gcv fully regression test.

Pan Li (4):
  RISC-V: Combine vec_duplicate + vaadd.vv to vaadd.vx on GR2VR cost
  RISC-V: Add test for vec_duplicate + vaadd.vv combine case 0 with GR2VR cost 
0, 1 and 15
  RISC-V: Add test for vec_duplicate + vaadd.vv combine case 1 with GR2VR cost 
0, 1 and 2
  RISC-V: Add test case for vaadd.vx combine polluting VXRM

 gcc/config/riscv/riscv-v.cc                   |   2 +
 gcc/config/riscv/riscv.cc                     |   1 +
 gcc/config/riscv/vector-iterators.md          |   8 +-
 .../riscv/rvv/autovec/vx_vf/vx-1-i16.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-1-i32.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-1-i64.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-1-i8.c         |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-2-i16.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-2-i32.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-2-i64.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-2-i8.c         |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-3-i16.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-3-i32.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-3-i64.c        |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-3-i8.c         |   1 +
 .../riscv/rvv/autovec/vx_vf/vx-4-i16.c        |   7 +
 .../riscv/rvv/autovec/vx_vf/vx-4-i32.c        |   6 +
 .../riscv/rvv/autovec/vx_vf/vx-4-i64.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-4-i8.c         |   6 +
 .../riscv/rvv/autovec/vx_vf/vx-5-i16.c        |   6 +
 .../riscv/rvv/autovec/vx_vf/vx-5-i32.c        |   6 +
 .../riscv/rvv/autovec/vx_vf/vx-5-i64.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-5-i8.c         |   6 +
 .../riscv/rvv/autovec/vx_vf/vx-5-u8.c         |   4 +-
 .../riscv/rvv/autovec/vx_vf/vx-6-i16.c        |   6 +
 .../riscv/rvv/autovec/vx_vf/vx-6-i32.c        |   6 +
 .../riscv/rvv/autovec/vx_vf/vx-6-i64.c        |   6 +
 .../riscv/rvv/autovec/vx_vf/vx-6-i8.c         |   6 +
 .../rvv/autovec/vx_vf/vx-fixed-vxrm-1-i16.c   |  23 ++
 .../rvv/autovec/vx_vf/vx-fixed-vxrm-1-i32.c   |  23 ++
 .../rvv/autovec/vx_vf/vx-fixed-vxrm-1-i64.c   |  23 ++
 .../rvv/autovec/vx_vf/vx-fixed-vxrm-1-i8.c    |  23 ++
 .../riscv/rvv/autovec/vx_vf/vx_binary.h       |  45 ++--
 .../riscv/rvv/autovec/vx_vf/vx_binary_data.h  | 196 ++++++++++++++++++
 .../rvv/autovec/vx_vf/vx_vaadd-run-1-i16.c    |  17 ++
 .../rvv/autovec/vx_vf/vx_vaadd-run-1-i32.c    |  17 ++
 .../rvv/autovec/vx_vf/vx_vaadd-run-1-i64.c    |  17 ++
 .../rvv/autovec/vx_vf/vx_vaadd-run-1-i8.c     |  17 ++
 38 files changed, 468 insertions(+), 25 deletions(-)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i16.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i64.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-fixed-vxrm-1-i8.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i16.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i64.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vaadd-run-1-i8.c

-- 
2.43.0