Public
Hi,
Could you please let us know if you have any comments
on this patch?
Kind regards,
Aleksandar Rakic
________________________________________
From: Aleksandar Rakic <aleksandar.ra...@htecgroup.com>
Sent: Monday, March 17, 2025 2:21 PM
To: gcc-patches@gcc.gnu.org
Cc: Djordje Todorovic; c...@mips.com; richard.guent...@gmail.com;
ja...@redhat.com; Matthew Fortune; Faraz Shahbazker; Aleksandar Rakic
Subject: [PATCH v2 03/12] Improve store_by_pieces_p
From: Matthew Fortune <matthew.fort...@imgtec.com>
gcc/
* config/mips/mips.cc (mips_store_by_pieces_p): Account for
LWL/LWR in store_by_pieces_p.
Cherry-picked 53d838794ad3379fdd8d1f3a812aa8f2dff56399
from https://github.com/MIPS/gcc
Signed-off-by: Matthew Fortune <matthew.fort...@imgtec.com>
Signed-off-by: Faraz Shahbazker <fshahbaz...@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.ra...@htecgroup.com>
---
gcc/config/mips/mips.cc | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index ae0477b2dce..7ff41862427 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -8407,7 +8407,7 @@ mips_store_by_pieces_p (unsigned HOST_WIDE_INT size,
unsigned int align)
LW/SWL/SWR sequence. This is often better than the 4 LIs and
4 SBs that we would generate when storing by pieces. */
if (align <= BITS_PER_UNIT)
- return size < 4;
+ return size < 4 || !ISA_HAS_LWL_LWR;
/* If the data is 2-byte aligned, then:
@@ -8442,7 +8442,9 @@ mips_store_by_pieces_p (unsigned HOST_WIDE_INT size,
unsigned int align)
(c4) A block move of 8 bytes can use two LW/SW sequences or a single
LD/SD sequence, and in these cases we've traditionally preferred
the memory copy over the more bulky constant moves. */
- return size < 8;
+ return (size < 8
+ || (align < 4 * BITS_PER_UNIT
+ && !ISA_HAS_LWL_LWR));
}
/* Emit straight-line code to move LENGTH bytes from SRC to DEST.
--
2.34.1
