Thumb2 add instructions of the form

        add     Rd, Rm

Are already 16-bit instructions, so turning them into

        adds    Rd, Rm

is pointless.

This patch adds support for this in the compiler and ensures that the
conversion to ADDS is skipped in this case.

The additional variant in arm.md is possibly redundant, but does mean
that we correctly calculate the length of this case and may even
encourage the compiler to try and reuse the source operation.

Tested on arm-eabi and applied to trunk.

R.
--- arm.c       (revision 190462)
+++ arm.c       (local)
@@ -13309,6 +13746,13 @@ thumb2_reorg (void)
                  switch (GET_CODE (src))
                    {
                    case PLUS:
+                     /* Adding two registers and storing the result
+                        in the first source is already a 16-bit
+                        operation.  */
+                     if (rtx_equal_p (dst, op0)
+                         && register_operand (op1, SImode))
+                       break;
+
                      if (low_register_operand (op0, SImode))
                        {
                          /* ADDS <Rd>,<Rn>,<Rm>  */
--- arm.md      (revision 190462)
+++ arm.md      (local)
@@ -746,11 +746,12 @@ (define_peephole2
 ;;  (plus (reg rN) (reg sp)) into (reg rN).  In this case reload will
 ;; put the duplicated register first, and not try the commutative version.
 (define_insn_and_split "*arm_addsi3"
-  [(set (match_operand:SI          0 "s_register_operand" "=r, k,r,r, k, r, 
k,k,r, k, r")
-       (plus:SI (match_operand:SI 1 "s_register_operand" "%rk,k,r,rk,k, 
rk,k,r,rk,k, rk")
-                (match_operand:SI 2 "reg_or_int_operand" "rI,rI,k,Pj,Pj,L, 
L,L,PJ,PJ,?n")))]
+  [(set (match_operand:SI          0 "s_register_operand" "=rk, r,k, r,r, k, 
r, k,k,r, k, r")
+       (plus:SI (match_operand:SI 1 "s_register_operand" "%0, rk,k, r,rk,k, 
rk,k,r,rk,k, rk")
+                (match_operand:SI 2 "reg_or_int_operand" "rk, rI,rI,k,Pj,Pj,L, 
L,L,PJ,PJ,?n")))]
   "TARGET_32BIT"
   "@
+   add%?\\t%0, %0, %2
    add%?\\t%0, %1, %2
    add%?\\t%0, %1, %2
    add%?\\t%0, %2, %1
@@ -773,9 +774,9 @@ (define_insn_and_split "*arm_addsi3"
                      operands[1], 0);
   DONE;
   "
-  [(set_attr "length" "4,4,4,4,4,4,4,4,4,4,16")
+  [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,16")
    (set_attr "predicable" "yes")
-   (set_attr "arch" "*,*,*,t2,t2,*,*,a,t2,t2,*")]
+   (set_attr "arch" "t2,*,*,*,t2,t2,*,*,a,t2,t2,*")]
 )
 
 (define_insn_and_split "*thumb1_addsi3"

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