From: Pan Li <pan2...@intel.com> The widen mul will have source type from N-bits to dest type 2N-bits. The previous check only focus on the HOST_WIDE_INT but not working for QI => HI, HI => SI and SI => DI. Thus, refine the widen mul precision check, aka dest has twice bits of input.
The below test suites are passed for this patch: 1. The rv32gcv fully regression tests. 2. The rv64gcv fully regression tests. 3. The x86 bootstrap tests. 4. The x86 fully regression tests. Pan Li (2): Match: Refine the widen mul check for SAT_MUL pattern RISC-V: Add testcase for rv32 SAT_MUL from uint64 gcc/match.pd | 3 +-- .../riscv/sat/sat_u_mul-1-u16-from-u64.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-1-u32-from-u64.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-1-u8-from-u64.c | 11 +++++++++++ .../riscv/sat/sat_u_mul-run-1-u16-from-u64.c | 16 ++++++++++++++++ .../riscv/sat/sat_u_mul-run-1-u32-from-u64.c | 16 ++++++++++++++++ .../riscv/sat/sat_u_mul-run-1-u8-from-u64.c | 16 ++++++++++++++++ 7 files changed, 82 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u16-from-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u32-from-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-1-u8-from-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u16-from-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u32-from-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-1-u8-from-u64.c -- 2.43.0
