Hi all, Similar to other patches in this series, this patch adds a splitter for DImode BSL1N operations, taking care to generate the right code in the GP regs case.
Thus for the testcase we generate:
bsl1n_gp:
eon x0, x0, x1
and x0, x0, x2
eor x0, x0, x1
ret
bsl1n_d:
bsl1n z0.d, z0.d, z1.d, z2.d
ret
instead of the previous:
bsl1n_gp: // The same, avoid moves to FP regs.
eon x0, x0, x1
and x0, x0, x2
eor x0, x0, x1
ret
bsl1n_d:
fmov x0, d0
fmov x1, d1
eon x0, x1, x0
fmov d31, x0
and v2.8b, v31.8b, v2.8b
eor v0.8b, v2.8b, v1.8b
ret
Bootstrapped and tested on aarch64-none-linux-gnu.
Ok for trunk?
Thanks,
Kyrill
Signed-off-by: Kyrylo Tkachov <ktkac...@nvidia.com>
gcc/
* config/aarch64/aarch64-sve2.md (*aarch64_sve2_bsl1n_unpreddi): New
define_insn_and_split.
gcc/testsuite/
* gcc.target/aarch64/sve2/bsl1n_d.c: New test.
0006-aarch64-Use-SVE2-BSL1N-for-DImode-arguments.patch
Description: 0006-aarch64-Use-SVE2-BSL1N-for-DImode-arguments.patch
