Resending due to difficulties with my email > On 7 Jul 2025, at 11:56, Kyrylo Tkachov <ktkac...@nvidia.com> wrote: > > Hi all, > > This series improves code generation for 64-bit vector types as well as the > scalar DImode types. > It makes use of SHA3 and SVE2 instructions like BCAX, EOR3, BSL*. > The first 2 patches just extend the mode iterators used in a straightforward > way. > Patches 3-7 handle the DImode cases to make sure we don’t force the operands > into > SIMD registers unnecessarily by introducing the appropriate splitters. > The final patch 7/7 is a bit more involved for reasons explained in the > description. > I don’t feel strongly about applying that patch, but if it’s acceptable or > can be adjusted > in a different way I’m happy to rework it. > > Bootstrapped and tested on aarch64-none-linux-gnu, with BOOT_CFLAGS having > -mcpu=grace > To exercise the SHA3 and SVE2 paths a bit more. > > Thanks, > Kyrill
