Spencer Abson <spencer.ab...@arm.com> writes: > This patch extends our vec_cmp expander to support partial FP modes. > > We use a predicate mode that is narrower the operation's VPRED to govern > unpacked FP operations under flag_trapping_math, so the expansion must > handle cases where the comparison's target and governing predicates have > different modes. > > While such predicates enable all of the defined part of the operation, they > are not all-true. Their false bits contribute to the (trapping) behavior of > the operation, so the operation itself should not have SVE_KNOWN_PTRUE. > > gcc/ChangeLog: > > * config/aarch64/aarch64-sve.md (vec_cmp<mode><vpred>): Extend > to handle partial FP modes. > (@aarch64_pred_fcm<cmp_op><mode>): Likewise. > (@aarch64_pred_fcmuo<mode>): Likewise. > * config/aarch64/aarch64-sve.md (*one_cmpl<mode>3): Rename to... > (@aarch64_pred_one_cmpl<mode>_z): ... this. > * config/aarch64/aarch64.cc (aarch64_emit_sve_fp_cond): Allow the > target and governing predicates to have different modes. > (aarch64_emit_sve_or_fp_conds): Likewise. > (aarch64_emit_sve_invert_fp_cond): Likewise. > (aarch64_expand_sve_vec_cmp_float): Likewise. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/sve/unpacked_fcm_1.c: New test. > * gcc.target/aarch64/sve/unpacked_fcm_2.c: Likewise.
OK, thanks. Richard
