On Tue, 1 Jul 2025, Umesh Kalappa wrote: > *config/riscv/riscv-cores.def(RISCV_CORE):Updated the supported march. > *config/riscv/riscv-ext-mips.def(DEFINE_RISCV_EXT): > New file added for mips conditional mov extension. > *config/riscv/riscv-ext.def: Likewise. > *config/riscv/t-riscv:Generates riscv-ext.opt > *config/riscv/riscv-ext.opt: Generated file. > *config/riscv/riscv.cc(riscv_expand_conditional_move):Updated for mips > cmov > and outlined some code that handle arch cond move. > *config/riscv/riscv.md(mov<mode>cc):updated expand for MIPS CCMOV. > *config/riscv/mips-insn.md:New file for mips-p8700 ccmov insn. > *testsuite/gcc.target/riscv/mipscondmov.c:Test file for mips.ccmov insn. > *gcc/doc/riscv-ext.texi:Updated for mips cmov.
You need to add spaces throughout this ChangeLog entry; cf. <https://www.gnu.org/prep/standards/standards.html#Style-of-Change-Logs>. Our commit hook may actually reject the entry as it stands. > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index bbc7547d385..2e14f084a5c 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -5468,6 +5472,68 @@ riscv_expand_conditional_branch (rtx label, rtx_code > code, rtx op0, rtx op1) > emit_jump_insn (gen_condjump (condition, label)); > } > > +/* canonicalization of the comparands. */ > +void > +canonicalize_comparands (rtx_code code, rtx *op0, rtx *op1) > +{ > + /* An integer comparison must be comparing WORD_MODE objects. > + Extend the comparison arguments as necessary. */ > + if ((INTEGRAL_MODE_P (GET_MODE (*op0)) && GET_MODE (*op0) != word_mode) > + || (INTEGRAL_MODE_P (GET_MODE (*op1)) && GET_MODE (*op1) != word_mode)) > + riscv_extend_comparands (code, op0, op1); > + > + /* We might have been handed back a SUBREG. Just to make things > + easy, force it into a REG. */ > + if (!REG_P (*op0) && !CONST_INT_P (*op0)) > + *op0 = force_reg (word_mode, *op0); > + if (!REG_P (*op1) && !CONST_INT_P (*op1)) > + *op1 = force_reg (word_mode, *op1); > +} > + > +/* Emit target specific conditional move like TARGET_XMIPSCMOV etc. */ > +bool > +riscv_target_conditional_move (rtx dest, rtx op0, rtx op1, rtx_code code, > + rtx cons, rtx alt) > +{ > + machine_mode dst_mode = GET_MODE (dest); > + rtx target; > + > + /* force the operands to the register. */ > + cons = force_reg (dst_mode, cons); > + alt = force_reg (dst_mode, alt); > + > + if (TARGET_XMIPSCMOV) > + { > + if (code == EQ || code == NE) > + { > + op0 = riscv_zero_if_equal (op0, op1); > + op1 = const0_rtx; > + } > + else > + { Still spaces here rather than a tab here, visible as misalignment between this brace and ones with the block immediately above. > + target = gen_reg_rtx (GET_MODE (op0)); > + riscv_emit_int_order_test (code, 0, target, op0, op1); > + op0 = target; > + op1 = const0_rtx; > + code = NE; > + } Likewise. FWIW I tend to run `s/ /\t/' over chunks of code being added or updated when I'm not sure white space is correct (or when I do know it's not, such as when pasted with gpm from another virtual console). How to apply that replacement will depend on the text editor you use. > + riscv_emit_int_compare (&code, &op0, &op1); > + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); > + emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (dst_mode, > + cond, cons, alt))); > + return true; > + } > + // TARGET_SFB_ALU || TARGET_XTHEADCONDMOV Do we allow C++-style comments nowadays? I think they used to be a no-no, but maybe it's not the case anymore. Maciej
