The "else operand" to maskload should always be a const_vector, never a
const_int.
This was just an issue I noticed while looking through the code, I don't
have a testcase which shows a concrete problem due to this.
Testing of that change alone showed ICEs with load lanes vectorization
and SVE. That turned out to be because the backend pattern was missing
a mode for the else operand (causing the middle-end to choose a
const_int during expansion), fixed thusly. That in turn exposed an
issue with the unpredicated load lanes expander which was using the
wrong mode for the else operand, so fixed that too.
Bootstrapped/tested on aarch64-linux-gnu, OK for trunk?
Thanks,
Alex
gcc/ChangeLog:
* config/aarch64/aarch64-sve.md
(vec_load_lanes<mode><vsingle>): Expand else operand in
subvector mode, as per optab documentation.
(vec_mask_load_lanes<mode><vsingle>): Add missing mode for
operand 3.
* config/aarch64/predicates.md (aarch64_maskload_else_operand):
Remove const_int.
---
gcc/config/aarch64/aarch64-sve.md | 4 ++--
gcc/config/aarch64/predicates.md | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 450975dd088..4aecb3a6bf8 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -1344,7 +1344,7 @@ (define_expand "vec_load_lanes<mode><vsingle>"
"TARGET_SVE"
{
operands[2] = aarch64_ptrue_reg (<VPRED>mode);
- operands[3] = CONST0_RTX (<MODE>mode);
+ operands[3] = CONST0_RTX (<VSINGLE>mode);
}
)
@@ -1354,7 +1354,7 @@ (define_insn "vec_mask_load_lanes<mode><vsingle>"
(unspec:SVE_STRUCT
[(match_operand:<VPRED> 2 "register_operand" "Upl")
(match_operand:SVE_STRUCT 1 "memory_operand" "m")
- (match_operand 3 "aarch64_maskload_else_operand")]
+ (match_operand:<VSINGLE> 3 "aarch64_maskload_else_operand")]
UNSPEC_LDN))]
"TARGET_SVE"
"ld<vector_count><Vesize>\t%0, %2/z, %1"
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index d8e9725a1b6..32056daf329 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -1076,5 +1076,5 @@ (define_predicate "aarch64_granule16_simm9"
&& !(INTVAL (op) & 0xf)")))
(define_predicate "aarch64_maskload_else_operand"
- (and (match_code "const_int,const_vector")
+ (and (match_code "const_vector")
(match_test "op == CONST0_RTX (GET_MODE (op))")))
