> On 17 Jun 2025, at 12:19, Kyrylo Tkachov <ktkac...@nvidia.com> wrote:
>
>
>
>> On 4 Apr 2025, at 20:28, ezra.sito...@arm.com wrote:
>>
>> From: Ezra Sitorus <ezra.sito...@arm.com>
>>
>> This patch updates `aarch64-sys-regs.def', bringing it into sync with
>> the Binutils source after this change:
>> https://sourceware.org/pipermail/binutils/2025-March/139894.html
>
> Ok. I think these changes are considered obvious.
> Do you need someone to push the patch for you?
>
I’ve pushed this patch to trunk after a bootstrap on aarch64-linux.
Thanks,
Kyrill
> Thanks,
> Kyrill
>
>>
>> gcc/ChangeLog:
>> * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
>> ---
>> Tested on aarch64-none-linux-gnu
>>
>> gcc/config/aarch64/aarch64-sys-regs.def | 16 ++++++++--------
>> 1 file changed, 8 insertions(+), 8 deletions(-)
>>
>> diff --git a/gcc/config/aarch64/aarch64-sys-regs.def
>> b/gcc/config/aarch64/aarch64-sys-regs.def
>> index 8b65673a5d6..dbfe3adf996 100644
>> --- a/gcc/config/aarch64/aarch64-sys-regs.def
>> +++ b/gcc/config/aarch64/aarch64-sys-regs.def
>> @@ -572,12 +572,12 @@
>> SYSREG ("mdrar_el1", CPENC (2,0,1,0,0), F_REG_READ, AARCH64_NO_FEATURES)
>> SYSREG ("mdscr_el1", CPENC (2,0,0,2,2), 0, AARCH64_NO_FEATURES)
>> SYSREG ("mdselr_el1", CPENC (2,0,0,4,2), F_ARCHEXT, AARCH64_FEATURE
>> (DEBUGv8p9))
>> - SYSREG ("mecid_a0_el2", CPENC (3,4,10,8,1), 0, AARCH64_NO_FEATURES)
>> - SYSREG ("mecid_a1_el2", CPENC (3,4,10,8,3), 0, AARCH64_NO_FEATURES)
>> - SYSREG ("mecid_p0_el2", CPENC (3,4,10,8,0), 0, AARCH64_NO_FEATURES)
>> - SYSREG ("mecid_p1_el2", CPENC (3,4,10,8,2), 0, AARCH64_NO_FEATURES)
>> - SYSREG ("mecid_rl_a_el3", CPENC (3,6,10,10,1), 0, AARCH64_NO_FEATURES)
>> - SYSREG ("mecidr_el2", CPENC (3,4,10,8,7), F_REG_READ, AARCH64_NO_FEATURES)
>> + SYSREG ("mecid_a0_el2", CPENC (3,4,10,8,1), F_ARCHEXT, AARCH64_FEATURE
>> (V8_7A))
>> + SYSREG ("mecid_a1_el2", CPENC (3,4,10,8,3), F_ARCHEXT, AARCH64_FEATURE
>> (V8_7A))
>> + SYSREG ("mecid_p0_el2", CPENC (3,4,10,8,0), F_ARCHEXT, AARCH64_FEATURE
>> (V8_7A))
>> + SYSREG ("mecid_p1_el2", CPENC (3,4,10,8,2), F_ARCHEXT, AARCH64_FEATURE
>> (V8_7A))
>> + SYSREG ("mecid_rl_a_el3", CPENC (3,6,10,10,1), F_ARCHEXT, AARCH64_FEATURE
>> (V8_7A))
>> + SYSREG ("mecidr_el2", CPENC (3,4,10,8,7), F_REG_READ|F_ARCHEXT,
>> AARCH64_FEATURE (V8_7A))
>> SYSREG ("mfar_el3", CPENC (3,6,6,0,5), 0, AARCH64_NO_FEATURES)
>> SYSREG ("midr_el1", CPENC (3,0,0,0,0), F_REG_READ, AARCH64_NO_FEATURES)
>> SYSREG ("mpam0_el1", CPENC (3,0,10,5,1), 0, AARCH64_NO_FEATURES)
>> @@ -1145,8 +1145,8 @@
>> SYSREG ("vbar_el2", CPENC (3,4,12,0,0), 0, AARCH64_NO_FEATURES)
>> SYSREG ("vbar_el3", CPENC (3,6,12,0,0), 0, AARCH64_NO_FEATURES)
>> SYSREG ("vdisr_el2", CPENC (3,4,12,1,1), F_ARCHEXT, AARCH64_FEATURE (RAS))
>> - SYSREG ("vmecid_a_el2", CPENC (3,4,10,9,1), 0, AARCH64_NO_FEATURES)
>> - SYSREG ("vmecid_p_el2", CPENC (3,4,10,9,0), 0, AARCH64_NO_FEATURES)
>> + SYSREG ("vmecid_a_el2", CPENC (3,4,10,9,1), F_ARCHEXT, AARCH64_FEATURE
>> (V8_7A))
>> + SYSREG ("vmecid_p_el2", CPENC (3,4,10,9,0), F_ARCHEXT, AARCH64_FEATURE
>> (V8_7A))
>> SYSREG ("vmpidr_el2", CPENC (3,4,0,0,5), 0, AARCH64_NO_FEATURES)
>> SYSREG ("vncr_el2", CPENC (3,4,2,2,0), F_ARCHEXT, AARCH64_FEATURE (V8_4A))
>> SYSREG ("vpidr_el2", CPENC (3,4,0,0,0), 0, AARCH64_NO_FEATURES)
>> --
>> 2.45.2
>>
>
