It corrects the shift type of interleaved stepped patterns for const vector
expanding in LRA. The shift instruction was initially LSHIFTRT, and it seems
still should be the same type for both LRA and other cases.
gcc/ChangeLog:
* config/riscv/riscv-v.cc
(expand_const_vector_interleaved_stepped_npatterns):
Fix ASHIFT to LSHIFTRT insn.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr120356.c: New test.
Signed-off-by: Alexey Merzlyakov <alexey.merzlya...@samsung.com>
---
gcc/config/riscv/riscv-v.cc | 2 +-
.../gcc.target/riscv/rvv/autovec/pr120356.c | 26 +++++++++++++++++++
2 files changed, 27 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index ac690df3688..59810e4314a 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1598,7 +1598,7 @@ expand_const_vector_interleaved_stepped_npatterns (rtx
target, rtx src,
shifted_vid = gen_reg_rtx (mode);
rtx shift = gen_int_mode (1, Xmode);
rtx shift_ops[] = {shifted_vid, vid, shift};
- emit_vlmax_insn (code_for_pred_scalar (ASHIFT, mode), BINARY_OP,
+ emit_vlmax_insn (code_for_pred_scalar (LSHIFTRT, mode), BINARY_OP,
shift_ops);
}
else
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c
new file mode 100644
index 00000000000..2913f04e4c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr120356.c
@@ -0,0 +1,26 @@
+/* { dg-do run } */
+/* { dg-require-effective-target rvv_zvl256b_ok } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -mrvv-vector-bits=zvl -O2"
} */
+
+unsigned char a = 5;
+long long c[18];
+
+static void d ()
+{
+ for (short i = 0; i < 60; i += 65413)
+ for (char j = 0; j < 18; j++)
+ {
+ for (char k = 0; k < 18; k++)
+ a *= 143;
+ for (char k = 0; k < 6; k++)
+ for (char l = 0; l < 18; l++)
+ c[l] = 0;
+ }
+}
+
+int main ()
+{
+ d ();
+ if (a + c[0] != 69)
+ __builtin_abort ();
+}
--
2.34.1
