[PATCH 3/7 v2] RISC-V: Add support for the XAndesbfhcvt ISA extension.

[KuanLin Chen]

Hi,

This extension defines instructions to perform scalar floating-point
conversion between the BFLOAT16 floating-point data and the IEEE-754
32-bit single-precision floating-point (SP) data in a scalar
floating point register.

gcc/ChangeLog:

        * config/riscv/andes.def: Add nds_fcvt_s_bf16 and nds_fcvt_bf16_s.
        * config/riscv/andes.md (riscv_nds_fcvt_bf16_s): New pattern.
        (riscv_nds_fcvt_s_bf16): New pattern.
        * config/riscv/riscv-builtins.cc: New AVAIL andesbfhcvt.
        Add new define RISCV_ATYPE_BF and RISCV_ATYPE_SF.
        * config/riscv/riscv-ftypes.def: New DEF_RISCV_FTYPE.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/xandesbfhcvt-1.c: New test.
        * gcc.target/riscv/xandesbfhcvt-2.c: New test.

0003-RISC-V-Add-support-for-the-XAndesbfhcvt-ISA-extensio.patch
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