On 18/06/2025 10:31, Alexandre Oliva wrote:
On Jun 9, 2025, "Richard Earnshaw (lists)" <richard.earns...@arm.com> wrote:
On 08/06/2025 14:15, Alexandre Oliva wrote:
VxWorks kernel mode doesn't support thumb code, so the test fails.
Require thumb2 support.
You already have -march=armv7, so that implies any thumb code will be
thumb2.
The parm of arm_thumb2_ok I'm interested in is the one about the
compiler's not issuing an error message when thumb mode is enabled, even
if implicitly by -march. arm-vx7r2 in kernel mode errors out with
-march=armv7, so there's no way to run the test there.
This is a compile-only test. In what way does vxworks kernel mode have
anything to do with this?
Please show me the exact options you're building the test with and the
errors you're getting. I'm just having to guess without that information.
I'll state again: this is a compile test. The target platform
environment really should have nothing to do with the behviour here.
So this doesn't really make sense as this is a compile-only
test. Furthermore, this will disable the test entirely if generating
Arm code. Is that really what you want?
Conceivably one could compile the test in arm mode, using a different
arch, but that wouldn't be a regression test, because the problem only
hit on thumb. So skipping it when thumb2 is not supported by the target
OS is indeed just what I had in mind.
Tested with arm-vx7r2 on gcc-14, where this came up, and with arm-eabi
on trunk. Absent objections, I'm going to install this as obvious in
the next few days.
Assuming your response counts as a potential objection, is the patch ok
to install now?
Not yet.
R.
Thanks,
for gcc/testsuite/ChangeLog
* g++.target/arm/pr120424.C: Require thumb2 support.
---
gcc/testsuite/g++.target/arm/pr120424.C | 1 +
1 file changed, 1 insertion(+)
diff --git a/gcc/testsuite/g++.target/arm/pr120424.C
b/gcc/testsuite/g++.target/arm/pr120424.C
index 4d0e49013c04a..620089ab56225 100644
--- a/gcc/testsuite/g++.target/arm/pr120424.C
+++ b/gcc/testsuite/g++.target/arm/pr120424.C
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-require-effective-target arm_thumb2_ok } */
/* { dg-options "-march=armv7 -O2 -fstack-clash-protection
-fnon-call-exceptions" } */
/* { dg-final { scan-assembler-not {#-8} } } */
/* LRA register elimination gets confused when register spilling
