According to the discussion in
https://gcc.gnu.org/pipermail/gcc-patches/2025-June/686893.html, by creating
a -mtune=generic may be a good idea to slove the question regarding the branch
cost.
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): Add "generic" tune.
(RISCV_CORE): Add "generic" core.
* config/riscv/riscv.cc: Add generic_tune_info.
* config/riscv/riscv.h (RISCV_TUNE_STRING_DEFAULT): Change default tune.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-default.c: New test.
*
gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c:
New test.
---
gcc/config/riscv/riscv-cores.def | 2 ++
gcc/config/riscv/riscv.cc | 23 +++++++++++++++++++
gcc/config/riscv/riscv.h | 2 +-
gcc/testsuite/gcc.target/riscv/mcpu-default.c | 18 +++++++++++++++
...Semantics_compare_reg_reg_return_reg_reg.c | 21 +++++++++++++++++
5 files changed, 65 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-default.c
create mode 100644
gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index cff7c77a0bd7..bb14819054af 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -33,6 +33,7 @@
#define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO)
#endif
+RISCV_TUNE("generic", generic, generic_tune_info)
RISCV_TUNE("rocket", generic, rocket_tune_info)
RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
@@ -78,6 +79,7 @@ RISCV_CORE("sifive-e31", "rv32imac", "sifive-3-series")
RISCV_CORE("sifive-e34", "rv32imafc", "sifive-3-series")
RISCV_CORE("sifive-e76", "rv32imafc", "sifive-7-series")
+RISCV_CORE("generic", "rv64gc", "generic")
RISCV_CORE("sifive-s21", "rv64imac", "rocket")
RISCV_CORE("sifive-s51", "rv64imac", "sifive-5-series")
RISCV_CORE("sifive-s54", "rv64imafdc", "sifive-5-series")
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 74462cc76a59..3d0632886200 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -450,6 +450,29 @@ static const struct cpu_vector_cost generic_vector_cost = {
&rvv_regmove_vector_cost, /* regmove */
};
+/* Costs to use when optimizing for generic. */
+static const struct riscv_tune_param generic_tune_info = {
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
+ {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
+ {COSTS_N_INSNS (33), COSTS_N_INSNS (65)}, /* int_div */
+ 1, /* issue_rate */
+ 4, /* branch_cost */
+ 5, /* memory_cost */
+ 8, /* fmv_cost */
+ true, /*
slow_unaligned_access */
+ false, /* vector_unaligned_access */
+ false, /* use_divmod_expansion */
+ false, /* overlap_op_by_pieces */
+ false, /* speculative_sched_vsetvl */
+ RISCV_FUSE_NOTHING, /* fusible_ops */
+ NULL, /* vector cost */
+ NULL, /* function_align */
+ NULL, /* jump_align */
+ NULL, /* loop_align */
+};
+
/* Costs to use when optimizing for rocket. */
static const struct riscv_tune_param rocket_tune_info = {
{COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 2759a4cb1c9f..45fa521f219f 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -43,7 +43,7 @@ along with GCC; see the file COPYING3. If not see
#endif
#ifndef RISCV_TUNE_STRING_DEFAULT
-#define RISCV_TUNE_STRING_DEFAULT "rocket"
+#define RISCV_TUNE_STRING_DEFAULT "generic"
#endif
extern const char *riscv_expand_arch (int argc, const char **argv);
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-default.c
b/gcc/testsuite/gcc.target/riscv/mcpu-default.c
new file mode 100644
index 000000000000..644d2e40daeb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/mcpu-default.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */
+/* { dg-options "-mcpu=generic -mabi=lp64d" } */
+/* generic => rv64gc */
+
+#if !((__riscv_xlen == 64) \
+ && !defined(__riscv_32e) \
+ && defined(__riscv_mul) \
+ && defined(__riscv_atomic) \
+ && (__riscv_flen == 64) \
+ && defined(__riscv_compressed))
+#error "unexpected arch"
+#endif
+
+int main()
+{
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c
b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c
new file mode 100644
index 000000000000..b759ab339dad
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/zicond-primitiveSemantics_compare_reg_reg_return_reg_reg.c
@@ -0,0 +1,21 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zicond -mabi=lp64d" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f" { target { rv32 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" "-O3" } } */
+
+#define N 10000
+
+int primitiveSemantics_compare_reg_reg_return_reg_reg_00(int *a, int min_v)
+{
+ int last = 0;
+
+ for (int i = 0; i < N; i++)
+ {
+ if (a[i] < min_v)
+ last = a[i];
+ }
+ return last;
+}
+
+/* { dg-final { scan-assembler-times {\mczero\.nez\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mczero\.eqz\M} 1 } } */
--
2.43.0
