On 6/10/25 2:55 PM, Vineet Gupta wrote:
On 6/10/25 13:35, Edwin Lu wrote:
The instruction scheduler appears to be speculatively hoisting vsetvl
insns outside of their basic block without checking for data
dependencies. This resulted in a situation where the following occurs
vsetvli a5,a1,e32,m1,tu,ma
vle32.v v2,0(a0)
sub a1,a1,a5 <-- a1 potentially set to 0
sh2add a0,a5,a0
vfmacc.vv v1,v2,v2
vsetvli a5,a1,e32,m1,tu,ma <-- incompatible vinfo. update vl to 0
beq a1,zero,.L12 <-- check if avl is 0
This patch would essentially delay the vsetvl update to after the branch
to prevent unnecessarily updating the vinfo at the end of a basic block.
PR 117974
gcc/ChangeLog:
* config/riscv/riscv.cc (struct riscv_tune_param): Add tune
param.
(riscv_sched_can_speculate_insn): Implement.
(TARGET_SCHED_CAN_SPECULATE_INSN): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/pr117974.c: New test.
Signed-off-by: Edwin Lu <e...@rivosinc.com>
---
V2: add testcase
V3: add opt flag to test performance
V4: change opt flag to tune param
V5: adjust test to prevent failures
[ ... Snip ... ]
Maybe add a one-liner comment on the need for removing funroll-loops (...not
related to patch per se but just to keep the test output stable...)
No need to resping/resend.
Yea, otherwise nobody's going to remember why that's in there ;-) OK
with that change.
jeff
