On Tue, 2025-06-10 at 16:55 +0800, mengqinggang wrote:
> Add a new movsi_internal_la32 similar to movsi_internal, change
> constraint w(m, k, ZC) to m.
"w" is defined as TARGET_MEM_CONSTRAINT, and per GCC Internal:
-- Macro: TARGET_MEM_CONSTRAINT
A single character to be used instead of the default ‘'m'’
character for general memory addresses. This defines the
constraint letter which matches the memory addresses accepted by
‘TARGET_LEGITIMATE_ADDRESS_P’. Define this macro if you want to
support new address formats in your back end without changing the
semantics of the ‘'m'’ constraint. This is necessary in order to
preserve functionality of inline assembly constructs using the
‘'m'’ constraint.
If I read the patches correctly:
* "LoongArch: Forbid ADDRESS_REG_REG in loongarch32" already makes
loongarch_legitimate_address_p reject k
* "LoongArch: Disable const_imm16_operand in loongarch_valid_offset_p"
already makes loongarch_legitimate_address_p reject ZC
Thus with those two patches on LA32 "w" is same as "m", so I don't think
this change is needed.
> movsi_internal_la32 used on LA32, movsi_internal used on LA64.
>
> gcc/ChangeLog:
>
> * config/loongarch/loongarch.md (*movsi_internal_la32): New.
> ---
> gcc/config/loongarch/loongarch.md | 24 ++++++++++++++++++++++--
> 1 file changed, 22 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/loongarch/loongarch.md
> b/gcc/config/loongarch/loongarch.md
> index c04f9eb9970..be273c0cc47 100644
> --- a/gcc/config/loongarch/loongarch.md
> +++ b/gcc/config/loongarch/loongarch.md
> @@ -2313,8 +2313,28 @@ (define_expand "movsi"
> (define_insn_and_split "*movsi_internal"
> [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,w,*f,f,*r,*m")
> (match_operand:SI 1 "move_operand" "r,Yd,w,rJ,*r*J,m,*f,*f"))]
> - "(register_operand (operands[0], SImode)
> - || reg_or_0_operand (operands[1], SImode))"
> + "TARGET_64BIT
> + && (register_operand (operands[0], SImode)
> + || reg_or_0_operand (operands[1], SImode))"
> + { return loongarch_output_move (operands); }
> + "CONST_INT_P (operands[1]) && REG_P (operands[0]) && GP_REG_P (REGNO
> + (operands[0]))"
> + [(const_int 0)]
> + "
> +{
> + loongarch_move_integer (operands[0], operands[0], INTVAL (operands[1]));
> + DONE;
> +}
> + "
> + [(set_attr "move_type" "move,const,load,store,mgtf,fpload,mftg,fpstore")
> + (set_attr "mode" "SI")])
> +
> +(define_insn_and_split "*movsi_internal_la32"
> + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,*f,f,*r,*m")
> + (match_operand:SI 1 "move_operand" "r,Yd,m,rJ,*r*J,m,*f,*f"))]
> + "TARGET_32BIT
> + && (register_operand (operands[0], SImode)
> + || reg_or_0_operand (operands[1], SImode))"
> { return loongarch_output_move (operands); }
> "CONST_INT_P (operands[1]) && REG_P (operands[0]) && GP_REG_P (REGNO
> (operands[0]))"
--
Xi Ruoyao <xry...@xry111.site> School of Aerospace Science and
Technology, Xidian University
