On Mon, Jun 09, 2025 at 12:21:16PM -0600, Jeff Law wrote: > > > On 6/9/25 9:43 AM, Stafford Horne wrote: > > > > > Hi, > > > > I do not have a fix for this yet. I feel using or1k_hard_regno_mode_ok to > > control allowing paradoxical subreging of openriscs sr_f special register > > is not > > right. It seems we would want to have something like > > or1k_regno_paradoxical_subreg_mode_ok. > > > > OpenRISC seems pretty unique in how we use (reg:BI 34 ?sr_f) for > > representing the > > condition register. The SR[F] bit is a flag bit in the supervisor register > > that > > represents if the last comparison was true (flag set) or false (flag unset). > Not sure it's that radically different than various other targets. It's > just a bit in a register. The question becomes how much to expose to GCC > and how to expose it. Reminds me a bit of the "T" register on the sh port.
Right, I think the point that is unique is that the SR[F] bit register is exposed to GCC as a BI mode register. Thanks for the tip on the SH T register, it does look very similar. Though, it is exposed to GCC as an SI register. Maybe that approach is better. -Stafford
