From: Pan Li <pan2...@intel.com>
Add asm dump check test for vec_duplicate + vor.vv combine to vor.vx,
with the GR2VR cost is 0, 2 and 15.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add test cases
for vor vx combine case 0 on GR2VR cost.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
data for vor.vx run test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i8.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u16.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u32.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u64.c: New test.
* gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u8.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
.../riscv/rvv/autovec/vx_vf/vx-1-i16.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-i32.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-i64.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-i8.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-1-u8.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-2-i16.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-2-i32.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-2-i64.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-2-i8.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-2-u16.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-2-u32.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-2-u64.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-2-u8.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-3-i16.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-3-i32.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-3-i64.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-3-i8.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-3-u16.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-3-u32.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-3-u64.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx-3-u8.c | 2 +
.../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 392 ++++++++++++++++++
.../rvv/autovec/vx_vf/vx_vor-run-1-i16.c | 15 +
.../rvv/autovec/vx_vf/vx_vor-run-1-i32.c | 15 +
.../rvv/autovec/vx_vf/vx_vor-run-1-i64.c | 15 +
.../riscv/rvv/autovec/vx_vf/vx_vor-run-1-i8.c | 15 +
.../rvv/autovec/vx_vf/vx_vor-run-1-u16.c | 15 +
.../rvv/autovec/vx_vf/vx_vor-run-1-u32.c | 15 +
.../rvv/autovec/vx_vf/vx_vor-run-1-u64.c | 15 +
.../riscv/rvv/autovec/vx_vf/vx_vor-run-1-u8.c | 15 +
33 files changed, 560 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u8.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index ad63a84c935..b15cb4cb8e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 87d7ecbb3fe..df3d3a33a34 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index 4a402e5fe2c..ed17b831577 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index b30c539f310..aa11dafc677 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
index fd3d726e7bd..15db5887a03 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
index 917e370cdc6..f15592c40eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
index 976a1b4687c..80e32afe843 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
index e96df13820b..9b19276f2e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
/* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vrsub.vx} 1 } } */
/* { dg-final { scan-assembler-times {vand.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vor.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index 4912dbf415e..596488c8770 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index 1219395bf30..8b4b7ebd289 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index 64604e228ee..544c9074a15 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index e6d5e633b7b..af53f2b9ca4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
index 35bf020705d..a8ff915d707 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
index 2c9d857dcbf..d587a88463e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
index ac49bffba63..ff205d53a55 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
index 8a3d027a57e..e8e2c7fb6e7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index b57d4e41b34..bd38b86bc55 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index 517fc0a3ed3..e0bdd2259fa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index 8ba77099f85..aab3b4afc7f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index e71127f4566..825988b04cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
index 82d96e9289b..a750510c1ce 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
index e19513ad18b..2d279cfa478 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
index 62a47ec14b0..5a90883c1df 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
index d693c367c91..69af97a3a99 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
@@ -9,8 +9,10 @@ DEF_VX_BINARY_CASE_0_WRAP(T, +, add)
DEF_VX_BINARY_CASE_0_WRAP(T, -, sub)
DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
+DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
/* { dg-final { scan-assembler-not {vadd.vx} } } */
/* { dg-final { scan-assembler-not {vsub.vx} } } */
/* { dg-final { scan-assembler-not {vrsub.vx} } } */
/* { dg-final { scan-assembler-not {vand.vx} } } */
+/* { dg-final { scan-assembler-not {vor.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index a5b4f954735..cd3cede15c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -1574,4 +1574,396 @@ uint64_t TEST_BINARY_DATA(uint64_t, and)[][3][N] =
},
};
+int8_t TEST_BINARY_DATA(int8_t, or)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xff, 0xff, 0xff, 0xff,
+ },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x3, 0x3, 0x3, 0x3,
+ 0x1, 0x1, 0x1, 0x1,
+ 0xff, 0xff, 0xff, 0xff,
+ },
+ },
+ {
+ { 0x7f },
+ {
+ 0x7f, 0x7f, 0x7f, 0x7f,
+ 0x80, 0x80, 0x80, 0x80,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x70, 0x70, 0x70, 0x70,
+ },
+ {
+ 0x7f, 0x7f, 0x7f, 0x7f,
+ 0xff, 0xff, 0xff, 0xff,
+ 0x7f, 0x7f, 0x7f, 0x7f,
+ 0x7f, 0x7f, 0x7f, 0x7f,
+ },
+ },
+ {
+ { 0xf0 },
+ {
+ 0xff, 0xff, 0xff, 0xff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x80, 0x80, 0x80, 0x80,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xf0, 0xf0, 0xf0, 0xf0,
+ 0xf1, 0xf1, 0xf1, 0xf1,
+ },
+ },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, or)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x3, 0x3, 0x3, 0x3,
+ 0x1, 0x1, 0x1, 0x1,
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ },
+ },
+ {
+ { 0x7fff },
+ {
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x8000, 0x8000, 0x8000, 0x8000,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x7000, 0x7000, 0x7000, 0x7000,
+ },
+ {
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ },
+ },
+ {
+ { 0xfff0 },
+ {
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ 0xfff0, 0xfff0, 0xfff0, 0xfff0,
+ 0xfff1, 0xfff1, 0xfff1, 0xfff1,
+ },
+ },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, or)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x3, 0x3, 0x3, 0x3,
+ 0x1, 0x1, 0x1, 0x1,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ },
+ {
+ { 0x7fffffff },
+ {
+ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+ 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x70000000, 0x70000000, 0x70000000, 0x70000000,
+ },
+ {
+ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+ },
+ },
+ {
+ { 0xfffffff0 },
+ {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xfffffff0, 0xfffffff0, 0xfffffff0, 0xfffffff0,
+ 0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1,
+ },
+ },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, or)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1,
0x1,
+ 0x2, 0x2, 0x2,
0x2,
+ 0x0, 0x0, 0x0,
0x0,
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ },
+ {
+ 0x1, 0x1, 0x1,
0x1,
+ 0x3, 0x3, 0x3,
0x3,
+ 0x1, 0x1, 0x1,
0x1,
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ },
+ },
+ {
+ { 0x7fffffffffffffffull },
+ {
+ 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
0x7fffffffffffffffull,
+ 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
0x8000000000000000ull,
+ 0xf, 0xf, 0xf,
0xf,
+ 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
0x7000000000000000ull,
+ },
+ {
+ 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
0x7fffffffffffffffull,
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
0x7fffffffffffffffull,
+ 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
0x7fffffffffffffffull,
+ },
+ },
+ {
+ { 0xfffffffffffffff0ull },
+ {
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ 0x1f, 0x1f, 0x1f,
0x1f,
+ 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
0x8000000000000000ull,
+ 0x1, 0x1, 0x1,
0x1,
+ },
+ {
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ 0xfffffffffffffff0ull, 0xfffffffffffffff0ull, 0xfffffffffffffff0ull,
0xfffffffffffffff0ull,
+ 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull,
0xfffffffffffffff1ull,
+ },
+ },
+};
+
+uint8_t TEST_BINARY_DATA(uint8_t, or)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xff, 0xff, 0xff, 0xff,
+ },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x3, 0x3, 0x3, 0x3,
+ 0x1, 0x1, 0x1, 0x1,
+ 0xff, 0xff, 0xff, 0xff,
+ },
+ },
+ {
+ { 0x7f },
+ {
+ 0x7f, 0x7f, 0x7f, 0x7f,
+ 0x80, 0x80, 0x80, 0x80,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x70, 0x70, 0x70, 0x70,
+ },
+ {
+ 0x7f, 0x7f, 0x7f, 0x7f,
+ 0xff, 0xff, 0xff, 0xff,
+ 0x7f, 0x7f, 0x7f, 0x7f,
+ 0x7f, 0x7f, 0x7f, 0x7f,
+ },
+ },
+ {
+ { 0xf0 },
+ {
+ 0xff, 0xff, 0xff, 0xff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x80, 0x80, 0x80, 0x80,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xf0, 0xf0, 0xf0, 0xf0,
+ 0xf1, 0xf1, 0xf1, 0xf1,
+ },
+ },
+};
+
+uint16_t TEST_BINARY_DATA(uint16_t, or)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x3, 0x3, 0x3, 0x3,
+ 0x1, 0x1, 0x1, 0x1,
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ },
+ },
+ {
+ { 0x7fff },
+ {
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x8000, 0x8000, 0x8000, 0x8000,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x7000, 0x7000, 0x7000, 0x7000,
+ },
+ {
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ },
+ },
+ {
+ { 0xfff0 },
+ {
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x8000, 0x8000, 0x8000, 0x8000,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ 0xffff, 0xffff, 0xffff, 0xffff,
+ 0xfff0, 0xfff0, 0xfff0, 0xfff0,
+ 0xfff1, 0xfff1, 0xfff1, 0xfff1,
+ },
+ },
+};
+
+uint32_t TEST_BINARY_DATA(uint32_t, or)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x2, 0x2, 0x2, 0x2,
+ 0x0, 0x0, 0x0, 0x0,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ {
+ 0x1, 0x1, 0x1, 0x1,
+ 0x3, 0x3, 0x3, 0x3,
+ 0x1, 0x1, 0x1, 0x1,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ },
+ },
+ {
+ { 0x7fffffff },
+ {
+ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+ 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+ 0xf, 0xf, 0xf, 0xf,
+ 0x70000000, 0x70000000, 0x70000000, 0x70000000,
+ },
+ {
+ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+ 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff,
+ },
+ },
+ {
+ { 0xfffffff0 },
+ {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0x1f, 0x1f, 0x1f, 0x1f,
+ 0x80000000, 0x80000000, 0x80000000, 0x80000000,
+ 0x1, 0x1, 0x1, 0x1,
+ },
+ {
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+ 0xfffffff0, 0xfffffff0, 0xfffffff0, 0xfffffff0,
+ 0xfffffff1, 0xfffffff1, 0xfffffff1, 0xfffffff1,
+ },
+ },
+};
+
+uint64_t TEST_BINARY_DATA(uint64_t, or)[][3][N] =
+{
+ {
+ { 0x1 },
+ {
+ 0x1, 0x1, 0x1,
0x1,
+ 0x2, 0x2, 0x2,
0x2,
+ 0x0, 0x0, 0x0,
0x0,
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ },
+ {
+ 0x1, 0x1, 0x1,
0x1,
+ 0x3, 0x3, 0x3,
0x3,
+ 0x1, 0x1, 0x1,
0x1,
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ },
+ },
+ {
+ { 0x7fffffffffffffffull },
+ {
+ 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
0x7fffffffffffffffull,
+ 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
0x8000000000000000ull,
+ 0xf, 0xf, 0xf,
0xf,
+ 0x7000000000000000ull, 0x7000000000000000ull, 0x7000000000000000ull,
0x7000000000000000ull,
+ },
+ {
+ 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
0x7fffffffffffffffull,
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
0x7fffffffffffffffull,
+ 0x7fffffffffffffffull, 0x7fffffffffffffffull, 0x7fffffffffffffffull,
0x7fffffffffffffffull,
+ },
+ },
+ {
+ { 0xfffffffffffffff0ull },
+ {
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ 0x1f, 0x1f, 0x1f,
0x1f,
+ 0x8000000000000000ull, 0x8000000000000000ull, 0x8000000000000000ull,
0x8000000000000000ull,
+ 0x1, 0x1, 0x1,
0x1,
+ },
+ {
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ 0xffffffffffffffffull, 0xffffffffffffffffull, 0xffffffffffffffffull,
0xffffffffffffffffull,
+ 0xfffffffffffffff0ull, 0xfffffffffffffff0ull, 0xfffffffffffffff0ull,
0xfffffffffffffff0ull,
+ 0xfffffffffffffff1ull, 0xfffffffffffffff1ull, 0xfffffffffffffff1ull,
0xfffffffffffffff1ull,
+ },
+ },
+};
+
#endif
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i16.c
new file mode 100644
index 00000000000..0a11aad97d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int16_t
+#define NAME or
+
+DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i32.c
new file mode 100644
index 00000000000..759ad2b6656
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int32_t
+#define NAME or
+
+DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i64.c
new file mode 100644
index 00000000000..1b3007ca09e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int64_t
+#define NAME or
+
+DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i8.c
new file mode 100644
index 00000000000..b0607443f72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-i8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T int8_t
+#define NAME or
+
+DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u16.c
new file mode 100644
index 00000000000..0dc8bee9b35
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint16_t
+#define NAME or
+
+DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u32.c
new file mode 100644
index 00000000000..8bc252853c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint32_t
+#define NAME or
+
+DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u64.c
new file mode 100644
index 00000000000..d286bdf7992
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint64_t
+#define NAME or
+
+DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u8.c
new file mode 100644
index 00000000000..dba433832fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vor-run-1-u8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T uint8_t
+#define NAME or
+
+DEF_VX_BINARY_CASE_0_WRAP(T, |, NAME)
+
+#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME,
out, in, x, n)
+
+#include "vx_binary_run.h"
--
2.43.0
