As Mark and I independently tripped, there's a Wuninitialized issue in
the RISC-V backend. While *I* know the value would always be properly
initialized, it'd be somewhat painful to either eliminate the infeasible
paths or do deep enough analysis to suppress the false positive.
So this initializes OUTPUT and verifies it's got a reasonable value
before using it for the final copy into operands[0].
Bootstrapped on the BPI (regression testing still has ~12hrs to go).
Pushing to the trunk.
Jeff
commit cbc258cd318756db8b5f0e4055dd8f1c1d618d22
Author: Jeff Law <j...@ventanamicro.com>
Date: Mon May 19 12:00:56 2025 -0600
[RISC-V] Fix false positive from Wuninitialized
As Mark and I independently tripped, there's a Wuninitialized issue in the
RISC-V backend. While *I* know the value would always be properly
initialized,
it'd be somewhat painful to either eliminate the infeasible paths or do deep
enough analysis to suppress the false positive.
So this initializes OUTPUT and verifies it's got a reasonable value before
using it for the final copy into operands[0].
Bootstrapped on the BPI (regression testing still has ~12hrs to go).
gcc/
* config/riscv/riscv.cc (synthesize_ior_xor): Initialize OUTPUT and
verify it's non-null before emitting the final copy insn.
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 54395b8d3a7..0b10842d176 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -14429,7 +14429,7 @@ synthesize_ior_xor (rtx_code code, rtx operands[3])
/* Synthesis is better than loading the constant. */
ival = INTVAL (operands[2]);
rtx input = operands[1];
- rtx output;
+ rtx output = NULL_RTX;
/* Emit the [x]ori insn that sets the low 11 bits into
the proper state. */
@@ -14458,6 +14458,8 @@ synthesize_ior_xor (rtx_code code, rtx operands[3])
input = output;
ival &= ~tmpval;
}
+
+ gcc_assert (output);
emit_move_insn (operands[0], output);
return true;
}