As we mentioned in GCC 15, we will remove avx10.1-256/512 in GCC 16.
Also, the combination of AVX10 and AVX512 option behavior will also be
simplified in GCC 16 since AVX10.1 now implied AVX512, making the
behavior matching everyone else.
gcc/ChangeLog:
* common/config/i386/cpuinfo.h
(get_available_features): Remove feature set for AVX10_1_256.
* common/config/i386/i386-common.cc
(OPTION_MASK_ISA2_AVX10_1_256_SET): Removed.
(OPTION_MASK_ISA_AVX10_1_SET): Imply all AVX512 features.
(OPTION_MASK_ISA2_AVX10_1_SET): Ditto.
(OPTION_MASK_ISA2_AVX2_UNSET): Remove AVX10_1_UNSET.
(OPTION_MASK_ISA2_AVX10_1_UNSET): Remove AVX10_1_256.
(OPTION_MASK_ISA2_AVX512F_UNSET): Unset AVX10_1.
(ix86_handle_option): Remove special handling for AVX512/AVX10.1
options, avx10_1_256. Modify ISA set for AVX10 options.
* common/config/i386/i386-cpuinfo.h
(enum feature_priority): Remove P_AVX10_1_256.
(enum processor_features): Remove FEATURE_AVX10_1_256.
* common/config/i386/i386-isas.h: Remove avx10.1-256/512.
* config/i386/driver-i386.cc (check_avx512_features): Removed.
(host_detect_local_cpu): Remove -march=native special handling.
* config/i386/i386-c.cc
(ix86_target_macros_internal): Remove AVX10_1_256.
* config/i386/i386-isa.def (AVX10_1_256): Removed.
* config/i386/i386-options.cc
(isa2_opts): Remove avx10.1-256.
(ix86_function_specific_save): Remove no_avx512_explicit and
no_avx10_1_explicit.
(ix86_function_specific_restore): Ditto.
(ix86_valid_target_attribute_inner_p): Remove avx10.1-256/512.
(ix86_valid_target_attribute_tree): Remove special handling
to rerun ix86_option_override_internal for AVX10.1-256.
(ix86_option_override_internal): Remove warning handling.
* config/i386/i386.h (PTA_GRANITERAPIDS): Use PTA_AVX10_1.
(PTA_DIAMONDRAPIDS): Use PTA_GRANITERAPIDS.
* config/i386/i386.opt: Remove ix86_no_avx512_explicit,
ix86_no_avx10_1_explicit, mavx10.1-256/512 and warning for
mavx10.1. Modify option comment.
* config/i386/i386.opt.urls: Remove avx10.1-256/512.
* doc/extend.texi: Remove avx10.1-256/512. Modify avx10.1 doc.
* doc/invoke.texi: Remove avx10.1-256/512 and evex512.
* doc/sourcebuild.texi: Remove avx10.1-256/512.
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx10_1-1.c: Remove warning.
* gcc.target/i386/avx10_1-2.c: Ditto.
* gcc.target/i386/avx10_1-3.c: Ditto.
* gcc.target/i386/avx10_1-4.c: Ditto.
* gcc.target/i386/pr111068.c: Ditto.
* gcc.target/i386/pr117946.c: Ditto.
* gcc.target/i386/avx10_1-11.c: Rename to ...
* gcc.target/i386/avx10_1-5.c: ... this. Remove warning.
* gcc.target/i386/avx10_1-12.c: Rename to ...
* gcc.target/i386/avx10_1-6.c: ... this. Remove warning.
* gcc.target/i386/avx10_1-26.c: Rename to ...
* gcc.target/i386/avx10_1-7.c: ... this. Remove warning.
The origin avx10_1-7.c is removed.
* gcc.target/i386/avx10_1-10.c: Removed.
* gcc.target/i386/avx10_1-13.c: Removed.
* gcc.target/i386/avx10_1-14.c: Removed.
* gcc.target/i386/avx10_1-15.c: Removed.
* gcc.target/i386/avx10_1-16.c: Removed.
* gcc.target/i386/avx10_1-17.c: Removed.
* gcc.target/i386/avx10_1-18.c: Removed.
* gcc.target/i386/avx10_1-19.c: Removed.
* gcc.target/i386/avx10_1-20.c: Removed.
* gcc.target/i386/avx10_1-21.c: Removed.
* gcc.target/i386/avx10_1-22.c: Removed.
* gcc.target/i386/avx10_1-23.c: Removed.
* gcc.target/i386/avx10_1-8.c: Removed.
* gcc.target/i386/avx10_1-9.c: Removed.
* gcc.target/i386/pr111889.c: Removed.
* gcc.target/i386/pr111907.c: Removed.
* gcc.target/i386/pr117304-1.c: Removed.
---
gcc/common/config/i386/cpuinfo.h | 2 -
gcc/common/config/i386/i386-common.cc | 63 +++-------
gcc/common/config/i386/i386-cpuinfo.h | 6 +-
gcc/common/config/i386/i386-isas.h | 2 -
gcc/config/i386/driver-i386.cc | 34 +-----
gcc/config/i386/i386-c.cc | 2 -
gcc/config/i386/i386-isa.def | 1 -
gcc/config/i386/i386-options.cc | 136 +--------------------
gcc/config/i386/i386.h | 17 +--
gcc/config/i386/i386.opt | 39 +-----
gcc/config/i386/i386.opt.urls | 9 --
gcc/doc/extend.texi | 15 +--
gcc/doc/invoke.texi | 10 +-
gcc/doc/sourcebuild.texi | 6 -
gcc/testsuite/gcc.target/i386/avx10_1-1.c | 1 -
gcc/testsuite/gcc.target/i386/avx10_1-10.c | 8 --
gcc/testsuite/gcc.target/i386/avx10_1-11.c | 7 --
gcc/testsuite/gcc.target/i386/avx10_1-12.c | 7 --
gcc/testsuite/gcc.target/i386/avx10_1-13.c | 14 ---
gcc/testsuite/gcc.target/i386/avx10_1-14.c | 13 --
gcc/testsuite/gcc.target/i386/avx10_1-15.c | 14 ---
gcc/testsuite/gcc.target/i386/avx10_1-16.c | 14 ---
gcc/testsuite/gcc.target/i386/avx10_1-17.c | 13 --
gcc/testsuite/gcc.target/i386/avx10_1-18.c | 14 ---
gcc/testsuite/gcc.target/i386/avx10_1-19.c | 14 ---
gcc/testsuite/gcc.target/i386/avx10_1-2.c | 1 -
gcc/testsuite/gcc.target/i386/avx10_1-20.c | 13 --
gcc/testsuite/gcc.target/i386/avx10_1-21.c | 8 --
gcc/testsuite/gcc.target/i386/avx10_1-22.c | 14 ---
gcc/testsuite/gcc.target/i386/avx10_1-23.c | 14 ---
gcc/testsuite/gcc.target/i386/avx10_1-26.c | 10 --
gcc/testsuite/gcc.target/i386/avx10_1-3.c | 1 -
gcc/testsuite/gcc.target/i386/avx10_1-4.c | 1 -
gcc/testsuite/gcc.target/i386/avx10_1-5.c | 5 +
gcc/testsuite/gcc.target/i386/avx10_1-6.c | 5 +
gcc/testsuite/gcc.target/i386/avx10_1-7.c | 12 +-
gcc/testsuite/gcc.target/i386/avx10_1-8.c | 6 -
gcc/testsuite/gcc.target/i386/avx10_1-9.c | 7 --
gcc/testsuite/gcc.target/i386/pr111068.c | 1 -
gcc/testsuite/gcc.target/i386/pr111889.c | 10 --
gcc/testsuite/gcc.target/i386/pr111907.c | 9 --
gcc/testsuite/gcc.target/i386/pr117304-1.c | 29 -----
gcc/testsuite/gcc.target/i386/pr117946.c | 1 -
43 files changed, 56 insertions(+), 552 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-10.c
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-11.c
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-12.c
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-13.c
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-14.c
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-15.c
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-16.c
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-17.c
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-18.c
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-19.c
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-20.c
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-21.c
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-22.c
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-23.c
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-26.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-5.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-6.c
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-8.c
delete mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-9.c
delete mode 100644 gcc/testsuite/gcc.target/i386/pr111889.c
delete mode 100644 gcc/testsuite/gcc.target/i386/pr111907.c
delete mode 100644 gcc/testsuite/gcc.target/i386/pr117304-1.c
diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h
index e7e575c79d4..c93ea07239a 100644
--- a/gcc/common/config/i386/cpuinfo.h
+++ b/gcc/common/config/i386/cpuinfo.h
@@ -1044,11 +1044,9 @@ get_available_features (struct __processor_model
*cpu_model,
/* Fall through. */
case 1:
set_feature (FEATURE_AVX10_1);
- set_feature (FEATURE_AVX10_1_256);
break;
default:
set_feature (FEATURE_AVX10_1);
- set_feature (FEATURE_AVX10_1_256);
break;
}
}
diff --git a/gcc/common/config/i386/i386-common.cc
b/gcc/common/config/i386/i386-common.cc
index 296df3b3230..4b04b1538de 100644
--- a/gcc/common/config/i386/i386-common.cc
+++ b/gcc/common/config/i386/i386-common.cc
@@ -119,9 +119,16 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F
#define OPTION_MASK_ISA2_EVEX512_SET OPTION_MASK_ISA2_EVEX512
#define OPTION_MASK_ISA2_USER_MSR_SET OPTION_MASK_ISA2_USER_MSR
-#define OPTION_MASK_ISA2_AVX10_1_256_SET OPTION_MASK_ISA2_AVX10_1_256
+#define OPTION_MASK_ISA_AVX10_1_SET \
+ (OPTION_MASK_ISA_AVX512F_SET | OPTION_MASK_ISA_AVX512CD_SET \
+ | OPTION_MASK_ISA_AVX512DQ_SET | OPTION_MASK_ISA_AVX512BW_SET \
+ | OPTION_MASK_ISA_AVX512VL_SET | OPTION_MASK_ISA_AVX512IFMA_SET \
+ | OPTION_MASK_ISA_AVX512VBMI_SET | OPTION_MASK_ISA_AVX512VBMI2_SET \
+ | OPTION_MASK_ISA_AVX512VNNI_SET | OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
+ | OPTION_MASK_ISA_AVX512BITALG_SET)
#define OPTION_MASK_ISA2_AVX10_1_SET \
- (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_1)
+ (OPTION_MASK_ISA2_AVX512FP16_SET | OPTION_MASK_ISA2_AVX512BF16_SET \
+ | OPTION_MASK_ISA2_AVX10_1)
#define OPTION_MASK_ISA2_AVX10_2_SET \
(OPTION_MASK_ISA2_AVX10_1_SET | OPTION_MASK_ISA2_AVX10_2)
#define OPTION_MASK_ISA2_AMX_AVX512_SET \
@@ -245,8 +252,7 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_AVX2_UNSET \
(OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \
| OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \
- | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET \
- | OPTION_MASK_ISA2_AVX10_1_UNSET)
+ | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET)
#define OPTION_MASK_ISA_AVX512F_UNSET \
(OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
| OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
@@ -323,8 +329,7 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512
#define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR
#define OPTION_MASK_ISA2_AVX10_1_UNSET \
- (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1 \
- | OPTION_MASK_ISA2_AVX10_2_UNSET)
+ (OPTION_MASK_ISA2_AVX10_1 | OPTION_MASK_ISA2_AVX10_2_UNSET)
#define OPTION_MASK_ISA2_AVX10_2_UNSET \
(OPTION_MASK_ISA2_AVX10_2 | OPTION_MASK_ISA2_AMX_AVX512_UNSET)
#define OPTION_MASK_ISA2_AMX_AVX512_UNSET OPTION_MASK_ISA2_AMX_AVX512
@@ -375,7 +380,8 @@ along with GCC; see the file COPYING3. If not see
#define OPTION_MASK_ISA2_AVX512F_UNSET \
(OPTION_MASK_ISA2_AVX512BW_UNSET \
- | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET)
+ | OPTION_MASK_ISA2_AVX512VP2INTERSECT_UNSET \
+ | OPTION_MASK_ISA2_AVX10_1_UNSET)
#define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
OPTION_MASK_ISA2_SSE_UNSET
#define OPTION_MASK_ISA2_AVX_UNSET \
@@ -632,7 +638,6 @@ ix86_handle_option (struct gcc_options *opts,
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
- opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -646,7 +651,6 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
- opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -865,7 +869,6 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
- opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -881,7 +884,6 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET;
- opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -895,7 +897,6 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
- opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -911,7 +912,6 @@ ix86_handle_option (struct gcc_options *opts,
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
opts->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
- opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -926,7 +926,6 @@ ix86_handle_option (struct gcc_options *opts,
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
opts->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512BITALG_UNSET;
- opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -942,7 +941,6 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET;
- opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -1010,7 +1008,6 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
- opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -1026,7 +1023,6 @@ ix86_handle_option (struct gcc_options *opts,
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET;
- opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -1040,7 +1036,6 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
- opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -1054,7 +1049,6 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
- opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -1068,7 +1062,6 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
- opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -1345,7 +1338,6 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_EVEX512_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_EVEX512_UNSET;
- opts->x_ix86_no_avx512_explicit = 1;
}
return true;
@@ -1362,35 +1354,18 @@ ix86_handle_option (struct gcc_options *opts,
}
return true;
- case OPT_mavx10_1_256:
- if (value)
- {
- opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_256_SET;
- opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_SET;
- opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
- opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
- }
- else
- {
- opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET;
- opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET;
- opts->x_ix86_no_avx10_1_explicit = 1;
- }
- return true;
-
case OPT_mavx10_1:
if (value)
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_SET;
- opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
- opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
}
else
{
opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_UNSET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_UNSET;
- opts->x_ix86_no_avx10_1_explicit = 1;
}
return true;
@@ -1399,8 +1374,8 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_2_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_2_SET;
- opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
- opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
}
else
{
@@ -1414,8 +1389,8 @@ ix86_handle_option (struct gcc_options *opts,
{
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AMX_AVX512_SET;
opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AMX_AVX512_SET;
- opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
- opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX10_1_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX10_1_SET;
}
else
{
diff --git a/gcc/common/config/i386/i386-cpuinfo.h
b/gcc/common/config/i386/i386-cpuinfo.h
index 6b2ab0a7671..c73a87dbbe2 100644
--- a/gcc/common/config/i386/i386-cpuinfo.h
+++ b/gcc/common/config/i386/i386-cpuinfo.h
@@ -148,8 +148,7 @@ enum feature_priority
P_AVX512F,
P_PROC_AVX512F,
P_X86_64_V4,
- P_AVX10_1_256,
- P_AVX10_1,
+ P_AVX10_1 = 34,
P_PROC_AVX10_1,
P_PROC_DYNAMIC
};
@@ -266,8 +265,7 @@ enum processor_features
FEATURE_SM4,
FEATURE_APX_F,
FEATURE_USER_MSR,
- FEATURE_AVX10_1_256,
- FEATURE_AVX10_1,
+ FEATURE_AVX10_1 = 114,
FEATURE_AVX10_2 = 116,
FEATURE_AMX_AVX512,
FEATURE_AMX_TF32,
diff --git a/gcc/common/config/i386/i386-isas.h
b/gcc/common/config/i386/i386-isas.h
index 55af985f160..379bb34ef3f 100644
--- a/gcc/common/config/i386/i386-isas.h
+++ b/gcc/common/config/i386/i386-isas.h
@@ -183,9 +183,7 @@ ISA_NAMES_TABLE_START
ISA_NAMES_TABLE_ENTRY("sm4", FEATURE_SM4, P_NONE, "-msm4")
ISA_NAMES_TABLE_ENTRY("apxf", FEATURE_APX_F, P_NONE, "-mapxf")
ISA_NAMES_TABLE_ENTRY("usermsr", FEATURE_USER_MSR, P_NONE, "-musermsr")
- ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_AVX10_1_256,
"-mavx10.1-256")
ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1, P_AVX10_1, "-mavx10.1")
- ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1, P_AVX10_1,
"-mavx10.1-512")
ISA_NAMES_TABLE_ENTRY("avx10.2", FEATURE_AVX10_2, P_NONE, "-mavx10.2")
ISA_NAMES_TABLE_ENTRY("amx-avx512", FEATURE_AMX_AVX512, P_NONE,
"-mamx-avx512")
diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc
index 1ff05e52ab3..63c7d79326d 100644
--- a/gcc/config/i386/driver-i386.cc
+++ b/gcc/config/i386/driver-i386.cc
@@ -374,33 +374,6 @@ detect_caches_intel (bool xeon_mp, unsigned max_level,
#define has_feature(f) \
has_cpu_feature (&cpu_model, cpu_features2, f)
-/* We will emit a warning when using AVX10.1 and AVX512 options with one
- enabled and the other disabled. Add this function to avoid push "-mno-"
- options under this scenario for -march=native. */
-
-bool check_avx512_features (__processor_model &cpu_model,
- unsigned int (&cpu_features2)[SIZE_OF_CPU_FEATURES],
- const enum processor_features feature)
-{
- if (has_feature (FEATURE_AVX10_1_256)
- && ((feature == FEATURE_AVX512F)
- || (feature == FEATURE_AVX512CD)
- || (feature == FEATURE_AVX512DQ)
- || (feature == FEATURE_AVX512BW)
- || (feature == FEATURE_AVX512VL)
- || (feature == FEATURE_AVX512IFMA)
- || (feature == FEATURE_AVX512VBMI)
- || (feature == FEATURE_AVX512VBMI2)
- || (feature == FEATURE_AVX512VNNI)
- || (feature == FEATURE_AVX512VPOPCNTDQ)
- || (feature == FEATURE_AVX512BITALG)
- || (feature == FEATURE_AVX512FP16)
- || (feature == FEATURE_AVX512BF16)))
- return false;
-
- return true;
-}
-
/* This will be called by the spec parser in gcc.cc when it sees
a %:local_cpu_detect(args) construct. Currently it will be
called with either "arch [32|64]" or "tune [32|64]" as argument
@@ -909,12 +882,7 @@ const char *host_detect_local_cpu (int argc, const char
**argv)
options = concat (options, " ",
isa_names_table[i].option, NULL);
}
- /* Never push -mno-avx10.1-{256,512} under -march=native to
- avoid unnecessary warnings when building libraries. */
- else if (isa_names_table[i].feature != FEATURE_AVX10_1_256
- && isa_names_table[i].feature != FEATURE_AVX10_1
- && check_avx512_features (cpu_model, cpu_features2,
- isa_names_table[i].feature))
+ else
options = concat (options, neg_option,
isa_names_table[i].option + 2, NULL);
}
diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc
index 0a320ca772a..213848ed390 100644
--- a/gcc/config/i386/i386-c.cc
+++ b/gcc/config/i386/i386-c.cc
@@ -733,8 +733,6 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__EVEX512__");
if (isa_flag2 & OPTION_MASK_ISA2_USER_MSR)
def_or_undef (parse_in, "__USER_MSR__");
- if (isa_flag2 & OPTION_MASK_ISA2_AVX10_1_256)
- def_or_undef (parse_in, "__AVX10_1_256__");
if (isa_flag2 & OPTION_MASK_ISA2_AVX10_1)
def_or_undef (parse_in, "__AVX10_1__");
if (isa_flag2 & OPTION_MASK_ISA2_APX_F)
diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def
index 19d78d7e44e..983299960cd 100644
--- a/gcc/config/i386/i386-isa.def
+++ b/gcc/config/i386/i386-isa.def
@@ -119,7 +119,6 @@ DEF_PTA(SM4)
DEF_PTA(APX_F)
DEF_PTA(USER_MSR)
DEF_PTA(EVEX512)
-DEF_PTA(AVX10_1_256)
DEF_PTA(AVX10_1)
DEF_PTA(AVX10_2)
DEF_PTA(AMX_AVX512)
diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc
index 45aa9b4b732..f743beb1948 100644
--- a/gcc/config/i386/i386-options.cc
+++ b/gcc/config/i386/i386-options.cc
@@ -261,7 +261,6 @@ static struct ix86_target_opts isa2_opts[] =
{ "-msm4", OPTION_MASK_ISA2_SM4 },
{ "-mevex512", OPTION_MASK_ISA2_EVEX512 },
{ "-musermsr", OPTION_MASK_ISA2_USER_MSR },
- { "-mavx10.1-256", OPTION_MASK_ISA2_AVX10_1_256 },
{ "-mavx10.1", OPTION_MASK_ISA2_AVX10_1 },
{ "-mavx10.2", OPTION_MASK_ISA2_AVX10_2 },
{ "-mamx-avx512", OPTION_MASK_ISA2_AMX_AVX512 },
@@ -713,8 +712,6 @@ ix86_function_specific_save (struct cl_target_option *ptr,
ptr->x_ix86_apx_features = opts->x_ix86_apx_features;
ptr->x_ix86_isa_flags_explicit = opts->x_ix86_isa_flags_explicit;
ptr->x_ix86_isa_flags2_explicit = opts->x_ix86_isa_flags2_explicit;
- ptr->x_ix86_no_avx512_explicit = opts->x_ix86_no_avx512_explicit;
- ptr->x_ix86_no_avx10_1_explicit = opts->x_ix86_no_avx10_1_explicit;
ptr->x_recip_mask_explicit = opts->x_recip_mask_explicit;
ptr->x_ix86_arch_string = opts->x_ix86_arch_string;
ptr->x_ix86_tune_string = opts->x_ix86_tune_string;
@@ -858,8 +855,6 @@ ix86_function_specific_restore (struct gcc_options *opts,
opts->x_ix86_apx_features = ptr->x_ix86_apx_features;
opts->x_ix86_isa_flags_explicit = ptr->x_ix86_isa_flags_explicit;
opts->x_ix86_isa_flags2_explicit = ptr->x_ix86_isa_flags2_explicit;
- opts->x_ix86_no_avx512_explicit = ptr->x_ix86_no_avx512_explicit;
- opts->x_ix86_no_avx10_1_explicit = ptr->x_ix86_no_avx10_1_explicit;
opts->x_recip_mask_explicit = ptr->x_recip_mask_explicit;
opts->x_ix86_arch_string = ptr->x_ix86_arch_string;
opts->x_ix86_tune_string = ptr->x_ix86_tune_string;
@@ -1133,9 +1128,7 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree
args, char *p_strings[],
IX86_ATTR_ISA ("apxf", OPT_mapxf),
IX86_ATTR_ISA ("evex512", OPT_mevex512),
IX86_ATTR_ISA ("usermsr", OPT_musermsr),
- IX86_ATTR_ISA ("avx10.1-256", OPT_mavx10_1_256),
IX86_ATTR_ISA ("avx10.1", OPT_mavx10_1),
- IX86_ATTR_ISA ("avx10.1-512", OPT_mavx10_1),
IX86_ATTR_ISA ("avx10.2", OPT_mavx10_2),
IX86_ATTR_ISA ("amx-avx512", OPT_mamx_avx512),
IX86_ATTR_ISA ("amx-tf32", OPT_mamx_tf32),
@@ -1429,18 +1422,6 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args,
target_clone_attr))
return error_mark_node;
- /* AVX10.1-256 will enable only 256 bit AVX512F features by setting all
- AVX512 related ISA flags and not setting EVEX512. When it is used
- with avx512 related function attribute, we need to enable 512 bit to
- align with the command line behavior. Manually set EVEX512 for this
- scenario. */
- if ((def->x_ix86_isa_flags2 & OPTION_MASK_ISA2_AVX10_1_256)
- && (opts->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512F)
- && (opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F)
- && !(def->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512)
- && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512))
- opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512;
-
/* If the changed options are different from the default, rerun
ix86_option_override_internal, and then save the options away.
The string options are attribute options, and will be undone
@@ -1451,10 +1432,7 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args,
|| option_strings[IX86_FUNCTION_SPECIFIC_ARCH]
|| option_strings[IX86_FUNCTION_SPECIFIC_TUNE]
|| enum_opts_set.x_ix86_fpmath
- || enum_opts_set.x_prefer_vector_width_type
- || (!(def->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_AVX10_1_256)
- && (opts->x_ix86_isa_flags2_explicit
- & OPTION_MASK_ISA2_AVX10_1_256)))
+ || enum_opts_set.x_prefer_vector_width_type)
{
/* If we are using the default tune= or arch=, undo the string assigned,
and use the default. */
@@ -2018,7 +1996,7 @@ ix86_option_override_internal (bool main_args_p,
struct gcc_options *opts_set)
{
unsigned int i;
- unsigned HOST_WIDE_INT ix86_arch_mask, avx512_isa_flags, avx512_isa_flags2;
+ unsigned HOST_WIDE_INT ix86_arch_mask;
const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
/* -mrecip options. */
@@ -2037,15 +2015,6 @@ ix86_option_override_internal (bool main_args_p,
{ "vec-sqrt", RECIP_MASK_VEC_SQRT },
};
- avx512_isa_flags = OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD
- | OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512BW
- | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512IFMA
- | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI2
- | OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VPOPCNTDQ
- | OPTION_MASK_ISA_AVX512BITALG;
- avx512_isa_flags2 = OPTION_MASK_ISA2_AVX512FP16
- | OPTION_MASK_ISA2_AVX512BF16;
-
/* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
if (TARGET_64BIT_DEFAULT && !TARGET_64BIT_P (opts->x_ix86_isa_flags))
@@ -2667,107 +2636,6 @@ ix86_option_override_internal (bool main_args_p,
&= ~((OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_BMI2 | OPTION_MASK_ISA_TBM)
& ~opts->x_ix86_isa_flags_explicit);
- /* Emit a warning if AVX10.1 options is used with AVX512/EVEX512 options
except
- for the following option combinations:
- 1. Both AVX10.1-512 and AVX512 with 512 bit vector width are enabled with
no
- explicit disable on other AVX512 features.
- 2. Both AVX10.1-256 and AVX512 w/o 512 bit vector width are enabled with
no
- explicit disable on other AVX512 features.
- 3. Both AVX10.1 and AVX512 are disabled. */
- if (TARGET_AVX10_1_P (opts->x_ix86_isa_flags2))
- {
- if (opts->x_ix86_no_avx512_explicit
- && (((~(avx512_isa_flags & opts->x_ix86_isa_flags)
- & (avx512_isa_flags & opts->x_ix86_isa_flags_explicit)))
- || ((~((avx512_isa_flags2 | OPTION_MASK_ISA2_EVEX512)
- & opts->x_ix86_isa_flags2)
- & ((avx512_isa_flags2 | OPTION_MASK_ISA2_EVEX512)
- & opts->x_ix86_isa_flags2_explicit)))))
- warning (0, "%<-mno-evex512%> or %<-mno-avx512XXX%> cannot disable "
- "AVX10 instructions when AVX10.1-512 is available in GCC
15, "
- "behavior will change to it will disable that part of "
- "AVX512 instructions since GCC 16");
- }
- else if (TARGET_AVX10_1_256_P (opts->x_ix86_isa_flags2))
- {
- if (TARGET_EVEX512_P (opts->x_ix86_isa_flags2)
- && (OPTION_MASK_ISA2_EVEX512 & opts->x_ix86_isa_flags2_explicit))
- {
- if (!TARGET_AVX512F_P (opts->x_ix86_isa_flags)
- || !(OPTION_MASK_ISA_AVX512F & opts->x_ix86_isa_flags_explicit))
- {
- /* We should not emit 512 bit instructions under AVX10.1-256
- when EVEX512 is enabled w/o any AVX512 features enabled.
- Disable EVEX512 bit for this. */
- warning (0, "Using %<-mevex512%> without any AVX512 features "
- "enabled together with AVX10.1 only will not enable "
- "any AVX512 or AVX10.1-512 features, using 256 as "
- "max vector size");
- opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_EVEX512;
- }
- else
- warning (0, "Vector size conflicts between AVX10.1 and AVX512, "
- "using 512 as max vector size");
- }
- else if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
- && (opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F)
- && !(OPTION_MASK_ISA2_EVEX512
- & opts->x_ix86_isa_flags2_explicit))
- warning (0, "Vector size conflicts between AVX10.1 and AVX512, using "
- "512 as max vector size");
- else if (opts->x_ix86_no_avx512_explicit
- && (((~(avx512_isa_flags & opts->x_ix86_isa_flags)
- & (avx512_isa_flags & opts->x_ix86_isa_flags_explicit)))
- || ((~(avx512_isa_flags2 & opts->x_ix86_isa_flags2)
- & (avx512_isa_flags2
- & opts->x_ix86_isa_flags2_explicit)))))
- warning (0, "%<-mno-avx512XXX%> cannot disable AVX10 instructions "
- "when AVX10 is available in GCC 15, behavior will change "
- "to it will disable that part of AVX512 instructions since "
- "GCC 16");
- }
- else if (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
- && (OPTION_MASK_ISA_AVX512F & opts->x_ix86_isa_flags_explicit))
- {
- if (opts->x_ix86_no_avx10_1_explicit
- && ((OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1)
- & opts->x_ix86_isa_flags2_explicit))
- {
- warning (0, "%<-mno-avx10.1-256, -mno-avx10.1-512%> cannot disable "
- "AVX512 instructions when %<-mavx512XXX%> in GCC 15, "
- "behavior will change to it will disable all the "
- "instructions in GCC 16");
- /* Reset those unset AVX512 flags set by AVX10 options when AVX10 is
- disabled. */
- if (OPTION_MASK_ISA2_AVX10_1_256 & opts->x_ix86_isa_flags2_explicit)
- {
- opts->x_ix86_isa_flags = (~avx512_isa_flags
- & opts->x_ix86_isa_flags)
- | (avx512_isa_flags & opts->x_ix86_isa_flags
- & opts->x_ix86_isa_flags_explicit);
- opts->x_ix86_isa_flags2 = (~avx512_isa_flags2
- & opts->x_ix86_isa_flags2)
- | (avx512_isa_flags2 & opts->x_ix86_isa_flags2
- & opts->x_ix86_isa_flags2_explicit);
- }
- }
- }
-
- /* Set EVEX512 if one of the following conditions meets:
- 1. AVX512 is enabled while EVEX512 is not explicitly set/unset.
- 2. AVX10.1-512 is enabled. */
- if (TARGET_AVX10_1_P (opts->x_ix86_isa_flags2)
- || (TARGET_AVX512F_P (opts->x_ix86_isa_flags)
- && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512)))
- opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512;
-
- /* Enable all AVX512 related ISAs when AVX10.1 is enabled. */
- if (TARGET_AVX10_1_256_P (opts->x_ix86_isa_flags2))
- {
- opts->x_ix86_isa_flags |= avx512_isa_flags;
- opts->x_ix86_isa_flags2 |= avx512_isa_flags2;
- }
-
/* Validate -mpreferred-stack-boundary= value or default it to
PREFERRED_STACK_BOUNDARY_DEFAULT. */
ix86_preferred_stack_boundary = PREFERRED_STACK_BOUNDARY_DEFAULT;
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 6a38de30de4..fca74639448 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2443,7 +2443,7 @@ constexpr wide_int_bitmask PTA_ALDERLAKE = PTA_TREMONT |
PTA_ADX | PTA_AVX
constexpr wide_int_bitmask PTA_SIERRAFOREST = PTA_ALDERLAKE | PTA_AVXIFMA
| PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD | PTA_ENQCMD |
PTA_UINTR;
constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS |
PTA_AMX_FP16
- | PTA_PREFETCHI;
+ | PTA_PREFETCHI | PTA_AVX10_1;
constexpr wide_int_bitmask PTA_GRANITERAPIDS_D = PTA_GRANITERAPIDS
| PTA_AMX_COMPLEX;
constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST;
@@ -2455,16 +2455,11 @@ constexpr wide_int_bitmask PTA_CLEARWATERFOREST =
PTA_SIERRAFOREST
| PTA_AVXVNNIINT16 | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_USER_MSR
| PTA_PREFETCHI;
constexpr wide_int_bitmask PTA_PANTHERLAKE = PTA_ARROWLAKE_S | PTA_PREFETCHI;
-constexpr wide_int_bitmask PTA_DIAMONDRAPIDS = PTA_SKYLAKE | PTA_PKU | PTA_SHA
- | PTA_GFNI | PTA_VAES | PTA_VPCLMULQDQ | PTA_RDPID | PTA_PCONFIG
- | PTA_WBNOINVD | PTA_CLWB | PTA_MOVDIRI | PTA_MOVDIR64B | PTA_ENQCMD
- | PTA_CLDEMOTE | PTA_PTWRITE | PTA_WAITPKG | PTA_SERIALIZE | PTA_TSXLDTRK
- | PTA_AMX_TILE | PTA_AMX_INT8 | PTA_AMX_BF16 | PTA_UINTR | PTA_AVXVNNI
- | PTA_AMX_FP16 | PTA_PREFETCHI | PTA_AMX_COMPLEX | PTA_AVX10_1_256
- | PTA_AVX10_1 | PTA_AVXIFMA | PTA_AVXNECONVERT | PTA_AVXVNNIINT16
- | PTA_AVXVNNIINT8 | PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4
- | PTA_AVX10_2 | PTA_APX_F | PTA_AMX_AVX512 | PTA_AMX_FP8 | PTA_AMX_TF32
- | PTA_AMX_TRANSPOSE | PTA_MOVRS | PTA_AMX_MOVRS | PTA_USER_MSR;
+constexpr wide_int_bitmask PTA_DIAMONDRAPIDS = PTA_GRANITERAPIDS_D
+ | PTA_AVXIFMA | PTA_AVXNECONVERT | PTA_AVXVNNIINT16 | PTA_AVXVNNIINT8
+ | PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_AVX10_2
+ | PTA_APX_F | PTA_AMX_AVX512 | PTA_AMX_FP8 | PTA_AMX_TF32 | PTA_AMX_TRANSPOSE
+ | PTA_MOVRS | PTA_AMX_MOVRS | PTA_USER_MSR;
constexpr wide_int_bitmask PTA_BDVER1 = PTA_64BIT | PTA_MMX | PTA_SSE
| PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 0abf13480f5..c93c0b1bb38 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -36,13 +36,6 @@ HOST_WIDE_INT ix86_isa_flags_explicit
Variable
HOST_WIDE_INT ix86_isa_flags2_explicit
-; Indicate if AVX512 and AVX10.1 are explicitly set no.
-Variable
-int ix86_no_avx512_explicit = 0
-
-Variable
-int ix86_no_avx10_1_explicit = 0
-
; Additional target flags
Variable
int ix86_target_flags
@@ -103,14 +96,6 @@ HOST_WIDE_INT x_ix86_isa_flags2_explicit
TargetSave
HOST_WIDE_INT x_ix86_isa_flags_explicit
-;; which flags were passed by the user
-TargetSave
-HOST_WIDE_INT x_ix86_no_avx512_explicit
-
-;; which flags were passed by the user
-TargetSave
-HOST_WIDE_INT x_ix86_no_avx10_1_explicit
-
;; whether -mtune was not specified
TargetSave
unsigned char tune_defaulted
@@ -1351,38 +1336,24 @@ mapx-inline-asm-use-gpr32
Target Var(ix86_apx_inline_asm_use_gpr32) Init(0)
Enable GPR32 in inline asm when APX_F enabled.
-mevex512
-Target Mask(ISA2_EVEX512) Var(ix86_isa_flags2) Save Warn(%<-mevex512%> will be
deprecated in GCC 16 due to all machines 512 bit vector size supported)
-Support 512 bit vector built-in functions and code generation.
-
musermsr
Target Mask(ISA2_USER_MSR) Var(ix86_isa_flags2) Save
Support USER_MSR built-in functions and code generation.
-mavx10.1-256
-Target Mask(ISA2_AVX10_1_256) Var(ix86_isa_flags2) Save Warn(%<-mavx10.1%> is
aliased to 512 bit since GCC14.3 and GCC15.1 while %<-mavx10.1-256%> and
%<-mavx10.1-512%> will be deprecated in GCC 16 due to all machines 512 bit
vector size supported)
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
-and AVX10.1-256 built-in functions and code generation.
-
mavx10.1
-Target Mask(ISA2_AVX10_1) Var(ix86_isa_flags2) Save Warn(%<-mavx10.1%> is
aliased to 512 bit since GCC14.3 and GCC15.1 while %<-mavx10.1-256%> and
%<-mavx10.1-512%> will be deprecated in GCC 16 due to all machines 512 bit
vector size supported)
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
-and AVX10.1-512 built-in functions and code generation.
-
-mavx10.1-512
-Target Alias(mavx10.1)
+Target Mask(ISA2_AVX10_1) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
-and AVX10.1-512 built-in functions and code generation.
+and AVX10.1 built-in functions and code generation.
mavx10.2
Target Mask(ISA2_AVX10_2) Var(ix86_isa_flags2) Save
Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
-AVX10.1-512 and AVX10.2 built-in functions and code generation.
+AVX10.1 and AVX10.2 built-in functions and code generation.
mamx-avx512
Target Mask(ISA2_AMX_AVX512) Var(ix86_isa_flags2) Save
-Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX10.1-512,
-AVX10.2 and AMX-AVX512 built-in functions and code generation.
+Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2,
+AVX10.1, AVX10.2 and AMX-AVX512 built-in functions and code generation.
mamx-tf32
Target Mask(ISA2_AMX_TF32) Var(ix86_isa_flags2) Save
diff --git a/gcc/config/i386/i386.opt.urls b/gcc/config/i386/i386.opt.urls
index 0d5a5a10119..cce524c232e 100644
--- a/gcc/config/i386/i386.opt.urls
+++ b/gcc/config/i386/i386.opt.urls
@@ -590,21 +590,12 @@ UrlSuffix(gcc/x86-Options.html#index-mapxf)
mapx-inline-asm-use-gpr32
UrlSuffix(gcc/x86-Options.html#index-mapx-inline-asm-use-gpr32)
-mevex512
-UrlSuffix(gcc/x86-Options.html#index-mevex512)
-
musermsr
UrlSuffix(gcc/x86-Options.html#index-musermsr)
-mavx10.1-256
-UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-256)
-
mavx10.1
UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1)
-mavx10.1-512
-UrlSuffix(gcc/x86-Options.html#index-mavx10_002e1-512)
-
mavx10.2
UrlSuffix(gcc/x86-Options.html#index-mavx10_002e2)
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index 212d2487558..93e5b760406 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -6684,23 +6684,10 @@ Enable/disable the generation of the USER_MSR
instructions.
Enable/disable the generation of the APX features, including
EGPR, PUSH2POP2, NDD and PPX.
-@cindex @code{target("avx10.1-256")} function attribute, x86
-@item avx10.1-256
-@itemx no-avx10.1-256
-Enable the generation of the AVX10.1 instructions with 256 bit support.
-Disable the generation of the AVX10.1 instructions.
-
@cindex @code{target("avx10.1")} function attribute, x86
@item avx10.1
@itemx no-avx10.1
-Enable the generation of the AVX10.1 instructions with 512 bit support.
-Disable the generation of the AVX10.1 instructions.
-
-@cindex @code{target("avx10.1-512")} function attribute, x86
-@item avx10.1-512
-@itemx no-avx10.1-512
-Enable the generation of the AVX10.1 instructions with 512 bit support.
-Disable the generation of the AVX10.1 instructions.
+Enable/Disable the generation of the AVX10.1 instructions.
@cindex @code{target("avx10.2")} function attribute, x86
@item avx10.2
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index f31d504f99e..b59ba36e0e9 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1496,8 +1496,8 @@ See RS/6000 and PowerPC Options.
-mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni -mamx-fp8
-mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16
-mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf
--musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mevex512 -mavx10.2
--mamx-avx512 -mamx-tf32 -mamx-transpose -mmovrs -mamx-movrs
+-musermsr -mavx10.1 -mavx10.2 -mamx-avx512 -mamx-tf32 -mamx-transpose -mmovrs
+-mamx-movrs
-mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops
-minline-stringops-dynamically -mstringop-strategy=@var{alg}
-mkl -mwidekl
@@ -36227,12 +36227,6 @@ preferred alignment to
@option{-mpreferred-stack-boundary=2}.
@opindex mavx10.1
@itemx -mavx10.1
@need 200
-@opindex mavx10.1-256
-@itemx -mavx10.1-256
-@need 200
-@opindex mavx10.1-512
-@itemx -mavx10.1-512
-@need 200
@opindex mavx10.2
@itemx -mavx10.2
@need 200
diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi
index 65eeeccb264..d8f5df554ac 100644
--- a/gcc/doc/sourcebuild.texi
+++ b/gcc/doc/sourcebuild.texi
@@ -2623,15 +2623,9 @@ Target supports compiling @code{avx} instructions.
@item avx_runtime
Target supports the execution of @code{avx} instructions.
-@item avx10.1-256
-Target supports the execution of @code{avx10.1-256} instructions.
-
@item avx10.1
Target supports the execution of @code{avx10.1} instructions.
-@item avx10.1-512
-Target supports the execution of @code{avx10.1-512} instructions.
-
@item avx10.2
Target supports the execution of @code{avx10.2} instructions.
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-1.c
b/gcc/testsuite/gcc.target/i386/avx10_1-1.c
index bd3249e6fc2..cfd9662bb13 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-1.c
@@ -1,6 +1,5 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
#include <immintrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-10.c
b/gcc/testsuite/gcc.target/i386/avx10_1-10.c
deleted file mode 100644
index dba2a4e0e2d..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-10.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1 -mavx512f -mno-evex512" } */
-/* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10
instructions when AVX10.1-512 is available" "" { target *-*-* } 0 } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
-/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines
512 bit vector size supported" "" { target *-*-* } 0 } */
-/* { dg-final { scan-assembler "%zmm" } } */
-
-#include "avx10_1-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-11.c
b/gcc/testsuite/gcc.target/i386/avx10_1-11.c
deleted file mode 100644
index 608817a45ab..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-11.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1 -mno-avx512f" } */
-/* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10
instructions when AVX10.1-512 is available" "" { target *-*-* } 0 } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
-/* { dg-final { scan-assembler "%zmm" } } */
-
-#include "avx10_1-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-12.c
b/gcc/testsuite/gcc.target/i386/avx10_1-12.c
deleted file mode 100644
index 1650f2682cb..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-12.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mno-avx10.1-512 -mavx512f" } */
-/* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512
instructions when '-mavx512XXX'" "" { target *-*-* } 0 } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
-/* { dg-final { scan-assembler "%zmm" } } */
-
-#include "avx10_1-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-13.c
b/gcc/testsuite/gcc.target/i386/avx10_1-13.c
deleted file mode 100644
index a864e96c262..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-13.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1-256" } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
-/* { dg-final { scan-assembler "%zmm" } } */
-
-typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
-
-__attribute__ ((target ("avx512f"))) __m512d
-foo ()
-{ /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512
as max vector size" } */
- __m512d a, b;
- a = a + b;
- return a;
-}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-14.c
b/gcc/testsuite/gcc.target/i386/avx10_1-14.c
deleted file mode 100644
index 76573e644fe..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-14.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx512f" } */
-/* { dg-final { scan-assembler "%zmm" } } */
-
-typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
-
-__attribute__ ((target ("avx10.1-256"))) __m512d
-foo ()
-{ /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512
as max vector size" } */
- __m512d a, b;
- a = a + b;
- return a;
-}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-15.c
b/gcc/testsuite/gcc.target/i386/avx10_1-15.c
deleted file mode 100644
index b227cf3e0ec..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-15.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1" } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
-/* { dg-final { scan-assembler "%zmm" } } */
-
-typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
-
-__attribute__ ((target ("avx512f,no-evex512"))) __m512d
-foo ()
-{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10
instructions when AVX10.1-512 is available" } */
- __m512d a, b;
- a = a + b;
- return a;
-}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-16.c
b/gcc/testsuite/gcc.target/i386/avx10_1-16.c
deleted file mode 100644
index b3fdb3f3d4f..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-16.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx512f -mno-evex512" } */
-/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines
512 bit vector size supported" "" { target *-*-* } 0 } */
-/* { dg-final { scan-assembler "%zmm" } } */
-
-typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
-
-__attribute__ ((target ("avx10.1"))) __m512d
-foo ()
-{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10
instructions when AVX10.1-512 is available" } */
- __m512d a, b;
- a = a + b;
- return a;
-}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-17.c
b/gcc/testsuite/gcc.target/i386/avx10_1-17.c
deleted file mode 100644
index 09f125215dc..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-17.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx512f" } */
-/* { dg-final { scan-assembler "%zmm" } } */
-
-typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
-
-__attribute__ ((target ("no-avx10.1-512"))) __m512d
-foo ()
-{ /* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512
instructions when '-mavx512XXX'" } */
- __m512d a, b;
- a = a + b;
- return a;
-}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-18.c
b/gcc/testsuite/gcc.target/i386/avx10_1-18.c
deleted file mode 100644
index c1edce8fede..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-18.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1" } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
-/* { dg-final { scan-assembler "%zmm" } } */
-
-typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
-
-__attribute__ ((target ("no-avx512f"))) __m512d
-foo ()
-{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10
instructions when AVX10.1-512 is available" } */
- __m512d a, b;
- a = a + b;
- return a;
-}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-19.c
b/gcc/testsuite/gcc.target/i386/avx10_1-19.c
deleted file mode 100644
index 25b58872a1a..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-19.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mno-avx10.1-512" } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
-/* { dg-final { scan-assembler "%zmm" } } */
-
-typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
-
-__attribute__ ((target ("avx512f"))) __m512d
-foo ()
-{ /* { dg-warning "'-mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512
instructions when '-mavx512XXX'" } */
- __m512d a, b;
- a = a + b;
- return a;
-}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-2.c
b/gcc/testsuite/gcc.target/i386/avx10_1-2.c
index 19962bc2a37..bf1de231a94 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-2.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-2.c
@@ -1,6 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-march=x86-64 -mavx10.1" } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
/* { dg-final { scan-assembler "%zmm" } } */
typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-20.c
b/gcc/testsuite/gcc.target/i386/avx10_1-20.c
deleted file mode 100644
index a2230654114..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-20.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mno-avx512f" } */
-/* { dg-final { scan-assembler "%zmm" } } */
-
-typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
-
-__attribute__ ((target ("avx10.1"))) __m512d
-foo ()
-{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10
instructions when AVX10.1-512 is available" } */
- __m512d a, b;
- a = a + b;
- return a;
-}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-21.c
b/gcc/testsuite/gcc.target/i386/avx10_1-21.c
deleted file mode 100644
index 2ae437e6ebf..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-21.c
+++ /dev/null
@@ -1,8 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1-256 -mevex512 -Wno-psabi" } */
-/* { dg-warning "Using '-mevex512' without any AVX512 features enabled
together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features,
using 256 as max vector size" "" { target *-*-* } 0 } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
-/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines
512 bit vector size supported" "" { target *-*-* } 0 } */
-/* { dg-final { scan-assembler-not "%zmm" } } */
-
-#include "avx10_1-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-22.c
b/gcc/testsuite/gcc.target/i386/avx10_1-22.c
deleted file mode 100644
index df7bffb1bdf..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-22.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1-256 -Wno-psabi" } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
-/* { dg-final { scan-assembler-not "%zmm" } } */
-
-typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
-
-__attribute__ ((target ("evex512"))) __m512d
-foo ()
-{ /* { dg-warning "Using '-mevex512' without any AVX512 features enabled
together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features,
using 256 as max vector size" "" { target *-*-* } 0 } */
- __m512d a, b;
- a = a + b;
- return a;
-}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-23.c
b/gcc/testsuite/gcc.target/i386/avx10_1-23.c
deleted file mode 100644
index 1f8458480fe..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-23.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mevex512 -Wno-psabi" } */
-/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines
512 bit vector size supported" "" { target *-*-* } 0 } */
-/* { dg-final { scan-assembler-not "%zmm" } } */
-
-typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__));
-
-__attribute__ ((target ("avx10.1-256"))) __m512d
-foo ()
-{ /* { dg-warning "Using '-mevex512' without any AVX512 features enabled
together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features,
using 256 as max vector size" "" { target *-*-* } 0 } */
- __m512d a, b;
- a = a + b;
- return a;
-}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-26.c
b/gcc/testsuite/gcc.target/i386/avx10_1-26.c
deleted file mode 100644
index d8874042da9..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-26.c
+++ /dev/null
@@ -1,10 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=x86-64-v3 -mavx512f" } */
-/* { dg-require-ifunc "" } */
-
-#include <immintrin.h>
-__attribute__((target_clones ("default","avx10.1")))
-__m512d foo(__m512d a, __m512d b)
-{
- return a + b;
-}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-3.c
b/gcc/testsuite/gcc.target/i386/avx10_1-3.c
index 992364af6d8..3be988a1a62 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-3.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-3.c
@@ -1,6 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
#include <immintrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-4.c
b/gcc/testsuite/gcc.target/i386/avx10_1-4.c
index b3d26032256..fbc92d5c4ca 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-4.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-4.c
@@ -1,6 +1,5 @@
/* { dg-do compile } */
/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
#include <immintrin.h>
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-5.c
b/gcc/testsuite/gcc.target/i386/avx10_1-5.c
new file mode 100644
index 00000000000..bada568ad94
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-5.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx10.1 -mno-avx512f -Wno-psabi" } */
+/* { dg-final { scan-assembler-not "%zmm" } } */
+
+#include "avx10_1-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-6.c
b/gcc/testsuite/gcc.target/i386/avx10_1-6.c
new file mode 100644
index 00000000000..192d1d1ae9a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-6.c
@@ -0,0 +1,5 @@
+/* { dg-do compile } */
+/* { dg-options "-march=x86-64 -mavx512f -mno-avx10.1" } */
+/* { dg-final { scan-assembler "%zmm" } } */
+
+#include "avx10_1-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-7.c
b/gcc/testsuite/gcc.target/i386/avx10_1-7.c
index fb74ffba087..d8874042da9 100644
--- a/gcc/testsuite/gcc.target/i386/avx10_1-7.c
+++ b/gcc/testsuite/gcc.target/i386/avx10_1-7.c
@@ -1,6 +1,10 @@
/* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1 -mavx512f" } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
-/* { dg-final { scan-assembler "%zmm" } } */
+/* { dg-options "-O2 -march=x86-64-v3 -mavx512f" } */
+/* { dg-require-ifunc "" } */
-#include "avx10_1-2.c"
+#include <immintrin.h>
+__attribute__((target_clones ("default","avx10.1")))
+__m512d foo(__m512d a, __m512d b)
+{
+ return a + b;
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-8.c
b/gcc/testsuite/gcc.target/i386/avx10_1-8.c
deleted file mode 100644
index dbb7d646032..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-8.c
+++ /dev/null
@@ -1,6 +0,0 @@
-/* { dg-do compile { target { ! ia32 } } } */
-/* { dg-options "-march=x86-64 -mavx10.1-256 -mavx512f -mno-evex512" } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
-/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines
512 bit vector size supported" "" { target *-*-* } 0 } */
-
-#include "avx10_1-1.c"
diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-9.c
b/gcc/testsuite/gcc.target/i386/avx10_1-9.c
deleted file mode 100644
index b95173892a4..00000000000
--- a/gcc/testsuite/gcc.target/i386/avx10_1-9.c
+++ /dev/null
@@ -1,7 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=x86-64 -mavx10.1-256 -mavx512f" } */
-/* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512
as max vector size" "" { target *-*-* } 0 } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
-/* { dg-final { scan-assembler "%zmm" } } */
-
-#include "avx10_1-2.c"
diff --git a/gcc/testsuite/gcc.target/i386/pr111068.c
b/gcc/testsuite/gcc.target/i386/pr111068.c
index 70c1e9a6b3b..49a853daf30 100644
--- a/gcc/testsuite/gcc.target/i386/pr111068.c
+++ b/gcc/testsuite/gcc.target/i386/pr111068.c
@@ -1,7 +1,6 @@
/* PR target/111068 */
/* { dg-do compile } */
/* { dg-options "-ffloat-store -mavx10.1" } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
typedef _Float16 __attribute__((__vector_size__ (8))) V;
V u, v, w;
diff --git a/gcc/testsuite/gcc.target/i386/pr111889.c
b/gcc/testsuite/gcc.target/i386/pr111889.c
deleted file mode 100644
index 4f7682a28b7..00000000000
--- a/gcc/testsuite/gcc.target/i386/pr111889.c
+++ /dev/null
@@ -1,10 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=x86-64" } */
-
-#include <immintrin.h>
-
-__attribute__ ((target ("no-evex512,avx512vl")))
-__m256d foo (__m256d __W, __mmask8 __U, __m256d __A)
-{
- return _mm256_mask_mov_pd (__W, __U, __A);
-}
diff --git a/gcc/testsuite/gcc.target/i386/pr111907.c
b/gcc/testsuite/gcc.target/i386/pr111907.c
deleted file mode 100644
index cadc9e45683..00000000000
--- a/gcc/testsuite/gcc.target/i386/pr111907.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-mavx512f -mno-evex512" } */
-/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines
512 bit vector size supported" "" { target *-*-* } 0 } */
-
-_Float128
-foo (_Float128 d, _Float128 e)
-{
- return __builtin_copysignf128 (d, e);
-}
diff --git a/gcc/testsuite/gcc.target/i386/pr117304-1.c
b/gcc/testsuite/gcc.target/i386/pr117304-1.c
deleted file mode 100644
index 58fb53cf29b..00000000000
--- a/gcc/testsuite/gcc.target/i386/pr117304-1.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* PR target/117304 */
-/* { dg-do compile } */
-/* { dg-options "-O2 -mavx512f -mno-evex512" } */
-/* { dg-warning "'-mevex512' will be deprecated in GCC 16 due to all machines
512 bit vector size supported" "" { target *-*-* } 0 } */
-
-typedef __attribute__((__vector_size__(32))) int __v8si;
-typedef __attribute__((__vector_size__(32))) unsigned int __v8su;
-typedef __attribute__((__vector_size__(64))) double __v8df;
-typedef __attribute__((__vector_size__(64))) int __v16si;
-typedef __attribute__((__vector_size__(64))) unsigned int __v16su;
-typedef __attribute__((__vector_size__(64))) float __v16sf;
-typedef float __m512 __attribute__ ((__vector_size__ (64), __may_alias__));
-
-volatile __v8df df;
-volatile __v16sf sf;
-volatile __v8si hi;
-volatile __v8su hui;
-volatile __v16si i;
-volatile __v16su ui;
-
-void
-foo()
-{
- hi ^= __builtin_ia32_cvttpd2dq512_mask(df, hi, 0, 4); /* { dg-error
"implicit declaration of function '__builtin_ia32_cvttpd2dq512_mask'; did you
mean '__builtin_ia32_\[^\n\r]*'?" } */
- hui ^= __builtin_ia32_cvttpd2udq512_mask(df, hui, 0, 4); /* { dg-error
"implicit declaration of function '__builtin_ia32_cvttpd2udq512_mask'; did you
mean '__builtin_ia32_\[^\n\r]*'?" } */
- ui ^= __builtin_ia32_cvttps2dq512_mask(sf, ui, 0, 4); /* { dg-error
"implicit declaration of function '__builtin_ia32_cvttps2dq512_mask'; did you
mean '__builtin_ia32_\[^\n\r]*'?" } */
- ui ^= __builtin_ia32_cvttps2udq512_mask(sf, ui, 0, 4); /* { dg-error
"implicit declaration of function '__builtin_ia32_cvttps2udq512_mask'; did you
mean '__builtin_ia32_\[^\n\r]*'?" } */
- __builtin_ia32_cvtudq2ps512_mask(ui, sf, 0, 4); /* { dg-error "implicit
declaration of function '__builtin_ia32_cvtudq2ps512_mask'; did you mean
'__builtin_ia32_\[^\n\r]*'?" } */
-}
diff --git a/gcc/testsuite/gcc.target/i386/pr117946.c
b/gcc/testsuite/gcc.target/i386/pr117946.c
index b46921cedaa..c36b4ef1bce 100644
--- a/gcc/testsuite/gcc.target/i386/pr117946.c
+++ b/gcc/testsuite/gcc.target/i386/pr117946.c
@@ -1,7 +1,6 @@
/* { dg-do compile { target { ! ia32 } } } */
/* { dg-require-effective-target dfp } */
/* { dg-options "-O -favoid-store-forwarding -mavx10.1 -mprefer-avx128
--param=store-forwarding-max-distance=128 -Wno-psabi" } */
-/* { dg-warning "'-mavx10.1' is aliased to 512 bit since GCC14.3 and GCC15.1
while '-mavx10.1-256' and '-mavx10.1-512' will be deprecated in GCC 16 due to
all machines 512 bit vector size supported" "" { target *-*-* } 0 } */
typedef __attribute__((__vector_size__ (64))) _Decimal32 V;
void
--
2.31.1
