Seems CI still fail:
Patch Status 46835-v4_RISCV_Fix_missing_implied_Zicsr_from_Zve32x-1 ·
Issue #3283 · ewlu/gcc-precommit-ci
<https://github.com/ewlu/gcc-precommit-ci/issues/3283>
/home/ewlu/precommit-03/_work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/predef-19.c:
In function 'main':
/home/ewlu/precommit-03/_work/gcc-precommit-ci/gcc-precommit-ci/riscv-gnu-toolchain/gcc/gcc/testsuite/gcc.target/riscv/predef-19.c:31:2:
error: #error "__riscv_zmmul"
riscv-gcc don't provide __riscv_zmmul .
@kito, there are __riscv_mul, __riscv_div, and __riscv_muldiv in GCC.
Should we enable __riscv_mul when we use zmmul extension ?
The Zve32x extension depends on the Zicsr extension.
Currently, enabling Zve32x alone does not automatically imply Zicsr in GCC.
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: Add Zve32x depends on Zicsr
gcc/testsuite/ChangeLog:
* gcc.target/riscv/predef-19.c: set the march to rv64im_zve32x
instead of rv64gc_zve32x to avoid Zicsr implied by g. Extra m is
added to avoid current 'V' extension requires 'M' extension
Signed-off-by: Jerry Zhang Jian<jerry.zhangj...@sifive.com>
---
gcc/common/config/riscv/riscv-common.cc | 1 +
gcc/testsuite/gcc.target/riscv/predef-19.c | 34 +++++-----------------
2 files changed, 8 insertions(+), 27 deletions(-)
diff --git a/gcc/common/config/riscv/riscv-common.cc
b/gcc/common/config/riscv/riscv-common.cc
index 15df22d5377..145a0f2bd95 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -137,6 +137,7 @@ static const riscv_implied_info_t riscv_implied_info[] =
{"zve64f", "f"},
{"zve64d", "d"},
+ {"zve32x", "zicsr"},
{"zve32x", "zvl32b"},
{"zve32f", "zve32x"},
{"zve32f", "zvl32b"},
diff --git a/gcc/testsuite/gcc.target/riscv/predef-19.c
b/gcc/testsuite/gcc.target/riscv/predef-19.c
index 2b90702192b..ca3d57abca9 100644
--- a/gcc/testsuite/gcc.target/riscv/predef-19.c
+++ b/gcc/testsuite/gcc.target/riscv/predef-19.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_zve32x -mabi=lp64d -mcmodel=medlow
-misa-spec=2.2" } */
+/* { dg-options "-O2 -march=rv64im_zve32x -mabi=lp64 -mcmodel=medlow
-misa-spec=2.2" } */
int main () {
@@ -15,50 +15,30 @@ int main () {
#error "__riscv_i"
#endif
-#if !defined(__riscv_c)
-#error "__riscv_c"
-#endif
-
#if defined(__riscv_e)
#error "__riscv_e"
#endif
-#if !defined(__riscv_a)
-#error "__riscv_a"
-#endif
-
#if !defined(__riscv_m)
#error "__riscv_m"
#endif
-#if !defined(__riscv_f)
-#error "__riscv_f"
-#endif
-
-#if !defined(__riscv_d)
-#error "__riscv_d"
-#endif
-
-#if defined(__riscv_v)
-#error "__riscv_v"
+#if !defined(__riscv_zicsr)
+#error "__riscv_zicsr"
#endif
-#if defined(__riscv_zvl128b)
-#error "__riscv_zvl128b"
+#if !defined(_riscv_zmmul)
+#error "__riscv_zmmul"
#endif
-#if defined(__riscv_zvl64b)
-#error "__riscv_zvl64b"
+#if !defined(__riscv_zve32x)
+#error "__riscv_zve32x"
#endif
#if !defined(__riscv_zvl32b)
#error "__riscv_zvl32b"
#endif
-#if !defined(__riscv_zve32x)
-#error "__riscv_zve32x"
-#endif
-
#if !defined(__riscv_vector)
#error "__riscv_vector"
#endif
-- 2.49.0
