Indu Bhagat <indu.bha...@oracle.com> writes:
> On 4/15/25 9:21 AM, Richard Sandiford wrote:
>> Indu Bhagat <indu.bha...@oracle.com> writes:
>>> Store Allocation Tags (st2g) is an Armv8.5-A memory tagging (MTE)
>>> instruction. It stores an allocation tag to two tag granules of memory.
>>>
>>> TBD:
>>> - Not too sure what is the best way to generate the st2g yet; A
>>> subsequent patch will emit them in one of the target hooks.
>>
>> Regarding the previous thread about this:
>>
>> https://gcc.gnu.org/pipermail/gcc-patches/2024-November/668671.html
>>
>
> Apologies for this one again slipping through the cracks.
>
>> and your question about whether all types of store tag instructions
>> should be volatile: if we went for that approach, then yeah, I think so.
>>
>> As I mentioned there, I don't think we should use (unspec ...) memory
>> addresses.
>>
>> But thinking more about it: can we guarantee that GCC will only use
>> these instruction patterns with base registers that are aligned to
>> 16 bytes? If so, then perhaps an alternative would be to model
>> them as read-modify-write operations to the whole granule (even though
>> the actual instructions leave normal memory untouched and only change
>> the tags). That is, rather than:
>>
>
> I think so. Each stack var is assigned a granule of its own (16-bytes);
> for alloca, we align explicitly; and each pointer is based off the SP
> (which is also 16-byte aligned for AAPCS64). IIRC, FEAT_MTE* are
> available in AArch64 only.
>
> BTW, the aarch64.md file has this comment for stg:
> ";; STG doesn't align the address but aborts with alignment fault
> ;; when the address is not 16-byte aligned."
Ah, yeah. So using a read-modify-rewrite TImode memory operation
should be fine in that case.
> Just curious: the same should be true for all MTE load/store tag
> instructions, isnt it ? I cant seem to find the above specific
> information in the ARM MTE instruction specification "Arm Architecture
> Reference Manual for A-profile architecture."...
In the pseudocode, this is done in the AArch64.MemTag accesses. E.g:
AArch64.MemTag[bits(64) address, AccessDescriptor accdesc_in] = bits(4) value
assert accdesc_in.tagaccess && !accdesc_in.tagchecked;
AddressDescriptor memaddrdesc;
AccessDescriptor accdesc = accdesc_in;
constant boolean aligned = IsAligned(address, TAG_GRANULE);
// Stores of allocation tags must be aligned
if !aligned then
constant FaultRecord fault = AlignmentFault(accdesc, address);
AArch64.Abort(fault);
Thanks,
Richard
