On Thu, May 1, 2025 at 12:49 AM H.J. Lu <hjl.to...@gmail.com> wrote: > > On Wed, Apr 30, 2025 at 7:48 PM Uros Bizjak <ubiz...@gmail.com> wrote: > > > > On Tue, Apr 29, 2025 at 11:40 PM H.J. Lu <hjl.to...@gmail.com> wrote: > > > > > > SMALL_REGISTER_CLASSES was added by > > > > > > commit c98f874233428d7e6ba83def7842fd703ac0ddf1 > > > Author: James Van Artsdalen <j...@gnu.org> > > > Date: Sun Feb 9 13:28:48 1992 +0000 > > > > > > Initial revision > > > > > > which became TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P. It is false from > > > day 1 for i386. Since x86-64 doubles the number of registers, Change > > > TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P to return false for x86-64 > > > and update decrease_live_ranges_number to skip hard register if > > > targetm.class_likely_spilled_p returns true. These extend the live > > > range of rbp, r8-r31 and xmm1-xmm31 registers. > > > > > > PR target/118996 > > > * ira.cc (decrease_live_ranges_number): Skip hard register if > > > targetm.class_likely_spilled_p returns true. > > > * config/i386/i386.cc (ix86_small_register_classes_for_mode_p): > > > New. > > > (TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P): Use it. > > > > Redeclaring X86_64 is too risky. We can perhaps enable integer > > registers for APX because it is a relatively new development. I'm > > undecided about AVX-512, perhaps this is worth a try. > > There are many GCC targets with 16 GPRs which don't return false > for TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P.
They don't have half of their available registers declared as "architectural" registers with assigned roles. Also, register allocation for x86_64 is fine-tuned with TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P, we are risking regressions if this is redefined. Uros.
