From: Pan Li <pan2...@intel.com>
This patch serices would like to support form 7 of the unsigned integer
SAT_ADD. Different to another forms of SAT_ADD, the form 7 will
leverage a wider type to tell overflow or not, aka:
#define DEF_SAT_U_ADD_FMT_7(WT, T) \
T __attribute__((noinline)) \
sat_u_add_##WT##_##T##_fmt_7(T x, T y) \
{ \
T max = -1; \
WT val = (WT)x + (WT)y; \
return val > max ? max : (T)val; \
}
WT is a wider type than T, and there is no additional change from
the middle-end besides match.pd.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
* The x86 bootstrap test.
* The x86 fully regression test.
Pan Li (3):
Match: Support form 7 for unsigned integer SAT_ADD
RISC-V: Add testcases for scalar unsigned integer SAT_ADD form 7
RISC-V: Add testcases for vector unsigned integer SAT_ADD form 7
gcc/match.pd | 16 +++-
.../riscv/rvv/autovec/sat/vec_sat_arith.h | 31 ++++++++
.../sat/vec_sat_u_add-9-u16-from-u32.c | 9 +++
.../sat/vec_sat_u_add-9-u16-from-u64.c | 9 +++
.../sat/vec_sat_u_add-9-u32-from-u64.c | 9 +++
.../autovec/sat/vec_sat_u_add-9-u8-from-u16.c | 9 +++
.../autovec/sat/vec_sat_u_add-9-u8-from-u32.c | 9 +++
.../autovec/sat/vec_sat_u_add-9-u8-from-u64.c | 9 +++
.../sat/vec_sat_u_add-run-9-u16-from-u32.c | 76 +++++++++++++++++++
.../sat/vec_sat_u_add-run-9-u16-from-u64.c | 76 +++++++++++++++++++
.../sat/vec_sat_u_add-run-9-u32-from-u64.c | 76 +++++++++++++++++++
.../sat/vec_sat_u_add-run-9-u8-from-u16.c | 76 +++++++++++++++++++
.../sat/vec_sat_u_add-run-9-u8-from-u32.c | 76 +++++++++++++++++++
.../sat/vec_sat_u_add-run-9-u8-from-u64.c | 76 +++++++++++++++++++
.../gcc.target/riscv/sat/sat_arith.h | 22 ++++++
.../riscv/sat/sat_u_add-7-u16-from-u32.c | 21 +++++
.../riscv/sat/sat_u_add-7-u16-from-u64.c | 21 +++++
.../riscv/sat/sat_u_add-7-u32-from-u64.c | 22 ++++++
.../riscv/sat/sat_u_add-7-u8-from-u16.c | 19 +++++
.../riscv/sat/sat_u_add-7-u8-from-u32.c | 19 +++++
.../riscv/sat/sat_u_add-7-u8-from-u64.c | 19 +++++
.../riscv/sat/sat_u_add-run-7-u16-from-u32.c | 26 +++++++
.../riscv/sat/sat_u_add-run-7-u16-from-u64.c | 26 +++++++
.../riscv/sat/sat_u_add-run-7-u32-from-u64.c | 26 +++++++
.../riscv/sat/sat_u_add-run-7-u8-from-u16.c | 26 +++++++
.../riscv/sat/sat_u_add-run-7-u8-from-u32.c | 26 +++++++
.../riscv/sat/sat_u_add-run-7-u8-from-u64.c | 26 +++++++
27 files changed, 855 insertions(+), 1 deletion(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u16-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u32-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-9-u8-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u16-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u32-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_add-run-9-u8-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u16-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u32-from-u64.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_add-7-u8-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u16-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u32-from-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/sat/sat_u_add-run-7-u8-from-u64.c
--
2.43.0
