Indu Bhagat <indu.bha...@oracle.com> writes: > Using post-index stg is a faster way of memory tagging/untagging. > > TBD: > - Currently generated by in the aarch64 backend. Not sure if this > is the right way to do it. > - Also not clear how to weave in the generation of stzg.
Similarly to patch 4, I think we should rewrite the existing stg pattern to use the same kind of approach that I mentioned in response to patch 2, then extend the predicate and constraint to support PRE_MODIFY and POST_MODIFY addresses. Thanks, Richard > > ChangeLog: > * gcc/config/aarch64/aarch64.md > > --- > > [New in RFC V2] > --- > gcc/config/aarch64/aarch64.md | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index 175aed3146ac..3cb773a77ad8 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -8475,6 +8475,21 @@ > [(set_attr "type" "memtag")] > ) > > +;; STG with post-index writeback. > +(define_insn "*stg_post" > + [(set (mem:QI (unspec:DI > + [(plus:DI (match_operand:DI 1 "register_operand" "=rk") > + (const_int 0))] > + UNSPEC_TAG_SPACE)) > + (and:QI (lshiftrt:DI (match_operand:DI 0 "register_operand" "rk") > + (const_int 56)) (const_int 15))) > + (set (match_dup 1) > + (plus:DI (match_dup 1) (match_operand:DI 2 > "aarch64_granule16_simm9" "i")))] > + "TARGET_MEMTAG" > + "stg\\t%0, [%1], #%2" > + [(set_attr "type" "memtag")] > +) > + > ;; ST2G updates allocation tags for two memory granules (i.e. 32 bytes) at > ;; once, without zero initialization. > (define_insn "st2g"
